/*
 * ARM Limited (ARM) is supplying this software for use with Cortex-M
 * processor based microcontroller, but can be equally used for other
 * suitable processor architectures. This file can be freely distributed.
 * Modifications to this file shall be clearly marked.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 * @file     CMS32M55xx.h
 * @brief    CMSIS HeaderFile
 * @version  1.2
 * @date     08. November 2019
 * @note     Generated by SVDConv V3.3.21 on Friday, 08.11.2019 11:21:37
 *           from File 'CMS32M55xx.svd',
 *           last modified on Friday, 08.11.2019 03:20:55
 */



/** @addtogroup CMS Ltd.
  * @{
  */


/** @addtogroup CMS32M55xx
  * @{
  */


#ifndef CMS32M55XX_H
#define CMS32M55XX_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M0 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* =========================================  CMS32M55xx Specific Interrupt Numbers  ========================================= */
  GPIO0_IRQn                =   0,              /*!< 0  P0[7:0] IRQ                                                            */
  GPIO1_IRQn                =   1,              /*!< 1  P1[7:0] IRQ                                                            */
  GPIO2_IRQn                =   2,              /*!< 2  P2[7:0] IRQ                                                            */
  GPIO3_IRQn                =   3,              /*!< 3  P3[7:0] IRQ                                                            */
  GPIO4_IRQn                =   4,              /*!< 4  P4[7:0] IRQ                                                            */
  CCP_IRQn                  =   6,              /*!< 6  Capture/PWM IRQ                                                        */
  ADC0_IRQn                 =   7,              /*!< 7  ADC0 IRQ                                                               */
  WWDT_IRQn                 =   9,              /*!< 9  WWDT IRQ                                                               */
  EPWM_IRQn                 =  10,              /*!< 10 EPWM IRQ                                                               */
  ADC1_IRQn                 =  12,              /*!< 12 ADC1 IRQ                                                               */
  ACMP_IRQn                 =  13,              /*!< 13 ACMP IRQ                                                               */
  UART0_IRQn                =  15,              /*!< 15 UART0 IRQ                                                              */
  UART1_IRQn                =  16,              /*!< 16 UART1 IRQ                                                              */
  TIMER0_IRQn               =  19,              /*!< 19 Timer0 IRQ                                                             */
  TIMER1_IRQn               =  20,              /*!< 20 Timer1 IRQ                                                             */
  WDT_IRQn                  =  23,              /*!< 23 Watchdog IRQ                                                           */
  I2C0_IRQn                 =  24,              /*!< 24 I2C IRQ                                                                */
  SSP0_IRQn                 =  26,              /*!< 26 SSP0 IRQ                                                               */
  SYS_CHK_IRQn              =  31               /*!< 31 SYS_CHK IRQ                                                            */
} IRQn_Type;



/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ===========================  Configuration of the ARM Cortex-M0 Processor and Core Peripherals  =========================== */
#define __CM0_REV                 0x0100U       /*!< CM0 Core Revision                                                         */
#define __NVIC_PRIO_BITS               2        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __MPU_PRESENT                  1        /*!< MPU present or not                                                        */
#define __FPU_PRESENT                  0        /*!< FPU present or not                                                        */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm0.h"                           /*!< ARM Cortex-M0 processor and core peripherals                              */
#include "system_CMS32M55xx.h"                  /*!< CMS32M55xx System                                                         */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                          SYSCON                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief SYSCON Decription (SYSCON)
  */

typedef struct {                                /*!< (@ 0x50000000) SYSCON Structure                                           */
  __IM  uint32_t  DID;                          /*!< (@ 0x00000000) DID Description                                            */
  __IOM uint32_t  AHBCKDIV;                     /*!< (@ 0x00000004) AHBCKDIV Description                                       */
  __IOM uint32_t  APBCKDIV;                     /*!< (@ 0x00000008) APBCKDIV Description                                       */
  __IOM uint32_t  APBCKEN;                      /*!< (@ 0x0000000C) APBCKEN Description                                        */
  __IOM uint32_t  CLKODIV;                      /*!< (@ 0x00000010) CLKODIV Description                                        */
  __IOM uint32_t  PCON;                         /*!< (@ 0x00000014) PCON Description                                           */
  __OM  uint32_t  RSTCON;                       /*!< (@ 0x00000018) RSTCON Description                                         */
  __IOM uint32_t  RSTSTAT;                      /*!< (@ 0x0000001C) RSTSTAT Description                                        */
  __IOM uint32_t  CLKCON;                       /*!< (@ 0x00000020) CLKCON Description                                         */
  __IOM uint32_t  CLKSEL;                       /*!< (@ 0x00000024) CLKSEL Description                                         */
  __IM  uint32_t  CLKSTAT;                      /*!< (@ 0x00000028) CLKSTAT Description                                        */
  __IOM uint32_t  APBCKSEL;                     /*!< (@ 0x0000002C) APBCKSEL Description                                       */
  __IM  uint32_t  IOMUX;                        /*!< (@ 0x00000030) IOMUX Description                                          */
  __IM  uint32_t  CIDL;                         /*!< (@ 0x00000034) CIDL Description                                           */
  __IM  uint32_t  CIDH;                         /*!< (@ 0x00000038) CIDH Description                                           */
  __IOM uint32_t  LVDCON;                       /*!< (@ 0x0000003C) LVDCON Description                                         */
  __IOM uint32_t  IOP00CFG;                     /*!< (@ 0x00000040) IOP00CFG Description                                       */
  __IOM uint32_t  IOP01CFG;                     /*!< (@ 0x00000044) IOP01CFG Description                                       */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  IOP04CFG;                     /*!< (@ 0x00000050) IOP04CFG Description                                       */
  __IOM uint32_t  IOP05CFG;                     /*!< (@ 0x00000054) IOP05CFG Description                                       */
  __IOM uint32_t  IOP06CFG;                     /*!< (@ 0x00000058) IOP06CFG Description                                       */
  __IOM uint32_t  IOP07CFG;                     /*!< (@ 0x0000005C) IOP07CFG Description                                       */
  __IOM uint32_t  IOP10CFG;                     /*!< (@ 0x00000060) IOP10CFG Description                                       */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  IOP12CFG;                     /*!< (@ 0x00000068) IOP12CFG Description                                       */
  __IOM uint32_t  IOP13CFG;                     /*!< (@ 0x0000006C) IOP13CFG Description                                       */
  __IOM uint32_t  IOP14CFG;                     /*!< (@ 0x00000070) IOP14CFG Description                                       */
  __IOM uint32_t  IOP15CFG;                     /*!< (@ 0x00000074) IOP15CFG Description                                       */
  __IOM uint32_t  IOP16CFG;                     /*!< (@ 0x00000078) IOP16CFG Description                                       */
  __IOM uint32_t  IOP17CFG;                     /*!< (@ 0x0000007C) IOP17CFG Description                                       */
  __IM  uint32_t  RESERVED2;
  __IOM uint32_t  IOP21CFG;                     /*!< (@ 0x00000084) IOP21CFG Description                                       */
  __IOM uint32_t  IOP22CFG;                     /*!< (@ 0x00000088) IOP22CFG Description                                       */
  __IOM uint32_t  IOP23CFG;                     /*!< (@ 0x0000008C) IOP23CFG Description                                       */
  __IOM uint32_t  IOP24CFG;                     /*!< (@ 0x00000090) IOP24CFG Description                                       */
  __IOM uint32_t  IOP25CFG;                     /*!< (@ 0x00000094) IOP25CFG Description                                       */
  __IOM uint32_t  IOP26CFG;                     /*!< (@ 0x00000098) IOP26CFG Description                                       */
  __IM  uint32_t  RESERVED3;
  __IOM uint32_t  IOP30CFG;                     /*!< (@ 0x000000A0) IOP30CFG Description                                       */
  __IOM uint32_t  IOP31CFG;                     /*!< (@ 0x000000A4) IOP31CFG Description                                       */
  __IOM uint32_t  IOP32CFG;                     /*!< (@ 0x000000A8) IOP32CFG Description                                       */
  __IM  uint32_t  RESERVED4;
  __IOM uint32_t  IOP34CFG;                     /*!< (@ 0x000000B0) IOP34CFG Description                                       */
  __IOM uint32_t  IOP35CFG;                     /*!< (@ 0x000000B4) IOP35CFG Description                                       */
  __IOM uint32_t  IOP36CFG;                     /*!< (@ 0x000000B8) IOP36CFG Description                                       */
  __IM  uint32_t  RESERVED5;
  __IOM uint32_t  IOP40CFG;                     /*!< (@ 0x000000C0) IOP40CFG Description                                       */
  __IM  uint32_t  RESERVED6[2];
  __IOM uint32_t  IOP43CFG;                     /*!< (@ 0x000000CC) IOP43CFG Description                                       */
  __IOM uint32_t  IOP44CFG;                     /*!< (@ 0x000000D0) IOP44CFG Description                                       */
  __IM  uint32_t  RESERVED7;
  __IOM uint32_t  IOP46CFG;                     /*!< (@ 0x000000D8) IOP46CFG Description                                       */
  __IOM uint32_t  IOP47CFG;                     /*!< (@ 0x000000DC) IOP47CFG Description                                       */
  __IM  uint32_t  RESERVED8[8];
  __IOM uint32_t  SYS_IMSC;                     /*!< (@ 0x00000100) SYS_IMSC Description                                       */
  __IM  uint32_t  SYS_RIS;                      /*!< (@ 0x00000104) SYS_RIS Description                                        */
  __IM  uint32_t  SYS_MIS;                      /*!< (@ 0x00000108) SYS_MIS Description                                        */
  __OM  uint32_t  SYS_ICLR;                     /*!< (@ 0x0000010C) SYS_ICLR Description                                       */
  __IOM uint32_t  HSI_TRIM;                     /*!< (@ 0x00000110) HSI_TRIM Description                                       */
  __IM  uint32_t  RESERVED9[39];
  __IOM uint32_t  SRAMLOCK;                     /*!< (@ 0x000001B0) SRAMLOCK Description                                       */
  __IM  uint32_t  RESERVED10[3];
  __IOM uint32_t  GPIO0LOCK;                    /*!< (@ 0x000001C0) GPIO0LOCK Description                                      */
  __IOM uint32_t  GPIO1LOCK;                    /*!< (@ 0x000001C4) GPIO1LOCK Description                                      */
  __IOM uint32_t  GPIO2LOCK;                    /*!< (@ 0x000001C8) GPIO2LOCK Description                                      */
  __IOM uint32_t  GPIO3LOCK;                    /*!< (@ 0x000001CC) GPIO3LOCK Description                                      */
  __IOM uint32_t  GPIO4LOCK;                    /*!< (@ 0x000001D0) GPIO4LOCK Description                                      */
  __IM  uint32_t  RESERVED11[10];
  __IOM uint32_t  IOCFGLOCK;                    /*!< (@ 0x000001FC) IOCFGLOCK Description                                      */
  __IM  uint32_t  RESERVED12[192];
  __IM  uint32_t  UIDX;                         /*!< (@ 0x00000500) UIDX Description                                           */
  __IM  uint32_t  RESERVED13[3];
  __IM  uint32_t  PCRCD;                        /*!< (@ 0x00000510) PCRCD Description                                          */
  __IM  uint32_t  RESERVED14[3];
  __IOM uint32_t  UUIDWC0;                      /*!< (@ 0x00000520) UUIDWC0 Description                                        */
  __IOM uint32_t  UUIDWC1;                      /*!< (@ 0x00000524) UUIDWC1 Description                                        */
  __IOM uint32_t  UUIDWC2;                      /*!< (@ 0x00000528) UUIDWC2 Description                                        */
  __IOM uint32_t  UUIDWCS;                      /*!< (@ 0x0000052C) UUIDWCS Description                                        */
} SYSCON_Type;                                  /*!< Size = 1328 (0x530)                                                       */

/*------AHBCKDIV------------------------------------------------------------*/
#define	SYS_AHBCKDIV_AHBDIV_Pos		(0)
#define SYS_AHBCKDIV_AHBDIV_Msk		(0xffUL<<SYS_AHBCKDIV_AHBDIV_Pos)
/*------APBCKDIV------------------------------------------------------------*/
#define	SYS_APBCKDIV_APBDIV_Pos		(0)
#define SYS_APBCKDIV_APBDIV_Msk		(0xffUL<<SYS_APBCKDIV_APBDIV_Pos)
/*------APBCKEN-------------------------------------------------------------*/
#define	SYS_APBCKEN_ADC1CE_Pos		(27)
#define SYS_APBCKEN_ADC1CE_Msk		(0x1UL<<SYS_APBCKEN_ADC1CE_Pos)
#define	SYS_APBCKEN_ACMPCE_Pos		(26)
#define SYS_APBCKEN_ACMPCE_Msk		(0x1UL<<SYS_APBCKEN_ACMPCE_Pos)
#define	SYS_APBCKEN_OPACE_Pos		(25)
#define SYS_APBCKEN_OPACE_Msk		(0x1UL<<SYS_APBCKEN_OPACE_Pos)
#define	SYS_APBCKEN_EPWMCE_Pos		(21)
#define SYS_APBCKEN_EPWMCE_Msk		(0x1UL<<SYS_APBCKEN_EPWMCE_Pos)
#define	SYS_APBCKEN_CRCCE_Pos		(20)
#define SYS_APBCKEN_CRCCE_Msk		(0x1UL<<SYS_APBCKEN_CRCCE_Pos)
#define	SYS_APBCKEN_WWDTCE_Pos		(14)
#define SYS_APBCKEN_WWDTCE_Msk		(0x1UL<<SYS_APBCKEN_WWDTCE_Pos)
#define	SYS_APBCKEN_CCPCE_Pos		(12)
#define SYS_APBCKEN_CCPCE_Msk		(0x1UL<<SYS_APBCKEN_CCPCE_Pos)
#define	SYS_APBCKEN_ADC0CE_Pos		(11)
#define SYS_APBCKEN_ADC0CE_Msk		(0x1UL<<SYS_APBCKEN_ADC0CE_Pos)
#define	SYS_APBCKEN_SPPCE_Pos		(9)
#define SYS_APBCKEN_SPPCE_Msk		(0x1UL<<SYS_APBCKEN_SPPCE_Pos)
#define	SYS_APBCKEN_I2CCE_Pos		(7)
#define SYS_APBCKEN_I2CCE_Msk		(0x1UL<<SYS_APBCKEN_I2CCE_Pos)
#define	SYS_APBCKEN_TIMER23CE_Pos	(6)
#define SYS_APBCKEN_TIMER23CE_Msk	(0x1UL<<SYS_APBCKEN_TIMER23CE_Pos)
#define	SYS_APBCKEN_UART1CE_Pos		(4)
#define SYS_APBCKEN_UART1CE_Msk		(0x1UL<<SYS_APBCKEN_UART1CE_Pos)
#define	SYS_APBCKEN_UART0CE_Pos		(3)
#define SYS_APBCKEN_UART0CE_Msk		(0x1UL<<SYS_APBCKEN_UART0CE_Pos)
#define	SYS_APBCKEN_HWDIVCE_Pos		(2)
#define SYS_APBCKEN_HWDIVCE_Msk		(0x1UL<<SYS_APBCKEN_HWDIVCE_Pos)
#define	SYS_APBCKEN_TIMER01CE_Pos	(1)
#define SYS_APBCKEN_TIMER01CE_Msk	(0x1UL<<SYS_APBCKEN_TIMER01CE_Pos)
#define	SYS_APBCKEN_WDTCE_Pos		(0)
#define SYS_APBCKEN_WDTCE_Msk		(0x1UL<<SYS_APBCKEN_WDTCE_Pos)
/*------CLKODIV-----------------------------------------------------------*/
#define	SYS_CLKODIV_CLKSEL_Pos		(9)
#define SYS_CLKODIV_CLKSEL_Msk		(0x3UL<<SYS_CLKODIV_CLKSEL_Pos)
#define	SYS_CLKODIV_EN_Pos			(8)
#define SYS_CLKODIV_EN_Msk			(0x1UL<<SYS_CLKODIV_EN_Pos)
#define	SYS_CLKODIV_DIV_Pos			(0)
#define SYS_CLKODIV_DIV_Msk			(0xffUL<<SYS_CLKODIV_DIV_Pos)
/*------PCON--------------------------------------------------------------*/
#define	SYS_PCON_KEY_Pos			(16)
#define SYS_PCON_KEY_Msk			(0xffffUL<<SYS_PCON_KEY_Pos)
#define	SYS_PCON_LDODS_Pos			(3)
#define SYS_PCON_LDODS_Msk			(0x1UL<<SYS_PCON_LDODS_Pos)
#define	SYS_PCON_STOP_Pos			(2)
#define SYS_PCON_STOP_Msk			(0x1UL<<SYS_PCON_STOP_Pos)
#define	SYS_PCON_DEEPSLEEP_Pos		(1)
#define SYS_PCON_DEEPSLEEP_Msk		(0x1UL<<SYS_PCON_DEEPSLEEP_Pos)
#define	SYS_PCON_SLEEP_Pos			(0)
#define SYS_PCON_SLEEP_Msk			(0x1UL<<SYS_PCON_SLEEP_Pos)
/*------RSTSTAT-----------------------------------------------------------*/
#define	SYS_RSTSTAT_CPURS_Pos		(2)
#define SYS_RSTSTAT_CPURS_Msk		(0x1UL<<SYS_RSTSTAT_CPURS_Pos)
#define	SYS_RSTSTAT_MCURS_Pos		(1)
#define SYS_RSTSTAT_MCURS_Msk		(0x1UL<<SYS_RSTSTAT_MCURS_Pos)
#define	SYS_RSTSTAT_WDTRS_Pos		(0)
#define SYS_RSTSTAT_WDTRS_Msk		(0x1UL<<SYS_RSTSTAT_WDTRS_Pos)
/*------CLKCON------------------------------------------------------------*/
#define	SYS_CLKCON_KEY_Pos			(16)
#define SYS_CLKCON_KEY_Msk			(0xffffUL<<SYS_CLKCON_KEY_Pos)
#define	SYS_CLKCON_IRCEN_Pos		(3)
#define SYS_CLKCON_IRCEN_Msk		(0x1UL<<SYS_CLKCON_IRCEN_Pos)
#define	SYS_CLKCON_IRCSEL_Pos		(0)
#define SYS_CLKCON_IRCSEL_Msk		(0x3UL<<SYS_CLKCON_IRCSEL_Pos)
/*------CLKSEL------------------------------------------------------------*/
#define	SYS_CLKSEL_KEY_Pos			(16)
#define SYS_CLKSEL_KEY_Msk			(0xffffUL<<SYS_CLKSEL_KEY_Pos)
#define	SYS_CLKSEL_CLKSEL_Pos		(0)
#define SYS_CLKSEL_CLKSEL_Msk		(0x3UL<<SYS_CLKSEL_CLKSEL_Pos)
/*------CLKSSTAT----------------------------------------------------------*/
#define	SYS_CLKSTAT_IRCSTB_Pos		(0)
#define SYS_CLKSTAT_IRCSTB_Msk		(0x1UL<<SYS_CLKSTAT_IRCSTB_Pos)
/*------APBCKSEL----------------------------------------------------------*/
#define	SYS_APBCKSEL_TMR01SEL_Pos	(0)
#define SYS_APBCKSEL_TMR01SEL_Msk	(0x3UL<<SYS_APBCKSEL_TMR01SEL_Pos)
/*------IOMUX-------------------------------------------------------------*/
#define	SYS_IOMUX_RESETPORT_Pos		(10)
#define SYS_IOMUX_RESETPORT_Msk		(0x3UL<<SYS_IOMUX_RESETPORT_Pos)
/*------LVDCON------------------------------------------------------------*/
#define	SYS_LVDCON_TSVEN_Pos		(11)
#define SYS_LVDCON_TSVEN_Msk		(0x1UL<<SYS_LVDCON_TSVEN_Pos)
#define	SYS_LVDCON_TSVAS_Pos		(10)
#define SYS_LVDCON_TSVAS_Msk		(0x1UL<<SYS_LVDCON_TSVAS_Pos)
#define	SYS_LVDCON_TSVADJ_Pos		(6)
#define SYS_LVDCON_TSVADJ_Msk		(0xFUL<<SYS_LVDCON_TSVADJ_Pos)
#define	SYS_LVDCON_LVDF_Pos			(5)
#define SYS_LVDCON_LVDF_Msk			(0x1UL<<SYS_LVDCON_LVDF_Pos)
#define	SYS_LVDCON_LVDE_Pos			(4)
#define SYS_LVDCON_LVDE_Msk			(0x1UL<<SYS_LVDCON_LVDE_Pos)
#define	SYS_LVDCON_SEL_Pos			(0)
#define SYS_LVDCON_SEL_Msk			(0x7UL<<SYS_LVDCON_SEL_Pos)


/*------IMSC--------------------------------------------------------------*/
#define	SYS_IMSC_LVDIMSC_Pos		(4)
#define SYS_IMSC_LVDIMSC_Msk		(0x1UL<<SYS_IMSC_LVDIMSC_Pos)
/*------RIS---------------------------------------------------------------*/
#define	SYS_RIS_LVDRIS_Pos			(4)
#define SYS_RIS_LVDRIS_Msk			(0x1UL<<SYS_RIS_LVDRIS_Pos)
/*------MIS---------------------------------------------------------------*/
#define	SYS_MIS_LVDMIS_Pos			(4)
#define SYS_MIS_LVDMIS_Msk			(0x1UL<<SYS_MIS_LVDMIS_Pos)
/*------ICLR--------------------------------------------------------------*/
#define	SYS_ICLR_LVDICLR_Pos		(4)
#define SYS_ICLR_LVDICLR_Msk		(0x1UL<<SYS_ICLR_LVDICLR_Pos)
/*------TRIM--------------------------------------------------------------*/
#define	SYS_TRIM_KEY_Pos			(16)
#define SYS_TRIM_KEY_Msk			(0xffffUL<<SYS_TRIM_KEY_Pos)
#define	SYS_TRIM_TRIM_Pos			(0)
#define SYS_TRIM_TRIM_Msk			(0xffUL<<SYS_TRIM_TRIM_Pos)
/*------SRAMLOCK----------------------------------------------------------*/
#define	SYS_SRAMLOCK_LOCK_Pos		(16)
#define SYS_SRAMLOCK_LOCK_Msk		(0xffffUL<<SYS_SRAMLOCK_LOCK_Pos)
#define	SYS_SRAMLOCK_REGION_Pos		(0)
#define SYS_SRAMLOCK_REGION_Msk		(0xfUL<<SYS_SRAMLOCK_REGION_Pos)
/* =========================================================================================================================== */
/* ================                                           GPIO0                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief GPIO0 Decription (GPIO0)
  */

typedef struct {                                /*!< (@ 0x52000000) GPIO0 Structure                                            */
  __IOM uint32_t  GPIO_PMS;                     /*!< (@ 0x00000000) GPIO_PMS Description                                       */
  __IOM uint32_t  GPIO_DOM;                     /*!< (@ 0x00000004) GPIO_DOM Description                                       */
  __IOM uint32_t  GPIO_DO;                      /*!< (@ 0x00000008) GPIO_DO Description                                        */
  __IM  uint32_t  GPIO_DI;                      /*!< (@ 0x0000000C) GPIO_DI Description                                        */
  __IOM uint32_t  GPIO_IMSC;                    /*!< (@ 0x00000010) GPIO_IMSC Description                                      */
  __IM  uint32_t  GPIO_RIS;                     /*!< (@ 0x00000014) GPIO_RIS Description                                       */
  __IM  uint32_t  GPIO_MIS;                     /*!< (@ 0x00000018) GPIO_MIS Description                                       */
  __OM  uint32_t  GPIO_ICLR;                    /*!< (@ 0x0000001C) GPIO_ICLR Description                                      */
  __IOM uint32_t  GPIO_ITYPE;                   /*!< (@ 0x00000020) GPIO_ITYPE Description                                     */
  __IOM uint32_t  GPIO_IVAL;                    /*!< (@ 0x00000024) GPIO_IVAL Description                                      */
  __IOM uint32_t  GPIO_IANY;                    /*!< (@ 0x00000028) GPIO_IANY Description                                      */
  __IOM uint32_t  GPIO_DIDB;                    /*!< (@ 0x0000002C) GPIO_DIDB Description                                      */
  __OM  uint32_t  GPIO_DOSET;                   /*!< (@ 0x00000030) GPIO_DOSET Description                                     */
  __OM  uint32_t  GPIO_DOCLR;                   /*!< (@ 0x00000034) GPIO_DOCLR Description                                     */
  __IOM uint32_t  GPIO_DR;                      /*!< (@ 0x00000038) GPIO_DR Description                                        */
  __IOM uint32_t  GPIO_SR;                      /*!< (@ 0x0000003C) GPIO_SR Description                                        */
} GPIO_Type;                                   /*!< Size = 64 (0x40)                                                          */

/*------PSM-----------------------------------------------------------------*/
#define	GPIO_PMS_PMS7_Pos		(28)
#define GPIO_PMS_PMS7_Msk		(0x7UL<<GPIO_PMS_PMS7_Pos)
#define	GPIO_PMS_PMS6_Pos		(24)
#define GPIO_PMS_PMS6_Msk		(0x7UL<<GPIO_PMS_PMS6_Pos)
#define	GPIO_PMS_PMS5_Pos		(20)
#define GPIO_PMS_PMS5_Msk		(0x7UL<<GPIO_PMS_PMS5_Pos)
#define	GPIO_PMS_PMS4_Pos		(16)
#define GPIO_PMS_PMS4_Msk		(0x7UL<<GPIO_PMS_PMS4_Pos)
#define	GPIO_PMS_PMS3_Pos		(12)
#define GPIO_PMS_PMS3_Msk		(0x7UL<<GPIO_PMS_PMS3_Pos)
#define	GPIO_PMS_PMS2_Pos		(8)
#define GPIO_PMS_PMS2_Msk		(0x7UL<<GPIO_PMS_PMS2_Pos)
#define	GPIO_PMS_PMS1_Pos		(4)
#define GPIO_PMS_PMS1_Msk		(0x7UL<<GPIO_PMS_PMS1_Pos)
#define	GPIO_PMS_PMS0_Pos		(0)
#define GPIO_PMS_PMS0_Msk		(0x7UL<<GPIO_PMS_PMS0_Pos)
/*------DIDB---------------------------------------------------------------*/
#define	GPIO_DIDB_DBCK_Pos		(8)
#define GPIO_DIDB_DBCK_Msk		(0x7UL<<GPIO_DIDB_DBCK_Pos)
#define	GPIO_DIDB_DIDB_Pos		(0)
#define GPIO_DIDB_DIDB_Msk		(0xffUL<<GPIO_DIDB_DIDB_Pos)

/* =========================================================================================================================== */
/* ================                                            WDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief WDT Decription (WDT)
  */

typedef struct {                                /*!< (@ 0x47800000) WDT Structure                                              */
  __IOM uint32_t  CON;                       /*!< (@ 0x00000000) WDTCON Description                                         */
  __IOM uint32_t  LOAD;                      /*!< (@ 0x00000004) WDTLOAD Description                                        */
  __IM  uint32_t  VAL;                       /*!< (@ 0x00000008) WDTVAL Description                                         */
  __IM  uint32_t  RIS;                       /*!< (@ 0x0000000C) WDTRIS Description                                         */
  __IM  uint32_t  MIS;                       /*!< (@ 0x00000010) WDTMIS Description                                         */
  __OM  uint32_t  ICLR;                      /*!< (@ 0x00000014) WDTICLR Description                                        */
  __IM  uint32_t  RESERVED[314];
  __IOM uint32_t  LOCK;                      /*!< (@ 0x00000500) WDTLOCK Description                                        */
} WDT_Type;                                     /*!< Size = 1284 (0x504)                                                       */

/*------WDTCON-------------------------------------------------------------*/
#define	WDT_WDTCON_DEBUG_Pos		(16)
#define WDT_WDTCON_DEBUG_Msk		(0x1UL<<WDT_WDTCON_DEBUG_Pos)
#define	WDT_WDTCON_WDTEN_Pos		(8)
#define WDT_WDTCON_WDTEN_Msk		(0xffUL<<WDT_WDTCON_WDTEN_Pos)
#define	WDT_WDTCON_WDTPRE_Pos		(2)
#define WDT_WDTCON_WDTPRE_Msk		(0x3UL<<WDT_WDTCON_WDTPRE_Pos)
#define	WDT_WDTCON_WDTIEN_Pos		(0)
#define WDT_WDTCON_WDTIEN_Msk		(0x1UL<<WDT_WDTCON_WDTIEN_Pos)
/*------WDTRIS-------------------------------------------------------------*/
#define	WDT_WDTRIS_WDTRIS_Pos		(0)
#define WDT_WDTRIS_WDTRIS_Msk		(0x1UL<<WDT_WDTRIS_WDTRIS_Pos)
/*------WDTMIS-------------------------------------------------------------*/
#define	WDT_WDTMIS_WDTMIS_Pos		(0)
#define WDT_WDTMIS_WDTMIS_Msk		(0x1UL<<WDT_WDTMIS_WDTMIS_Pos)

/* =========================================================================================================================== */
/* ================                                           WWDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief WWDT Decription (WWDT)
  */

typedef struct {                                /*!< (@ 0x41800000) WWDT Structure                                             */
  __IOM uint32_t  CON;                      /*!< (@ 0x00000000) WWDTCON Description                                        */
  __OM  uint32_t  RL;                       /*!< (@ 0x00000004) WWDTRL Description                                         */
  __IM  uint32_t  VAL;                      /*!< (@ 0x00000008) WWDTVAL Description                                        */
  __IM  uint32_t  RIS;                      /*!< (@ 0x0000000C) WWDTRIS Description                                        */
  __IM  uint32_t  MIS;                      /*!< (@ 0x00000010) WWDTMIS Description                                        */
  __OM  uint32_t  ICLR;                     /*!< (@ 0x00000014) WWDTICLR Description                                       */
} WWDT_Type;                                    /*!< Size = 24 (0x18)                                                          */

/*------WWDTCON------------------------------------------------------------*/
#define	WWDT_WWDTCON_DEBUG_Pos		(31)
#define WWDT_WWDTCON_DEBUG_Msk		(0x1UL<<WWDT_WWDTCON_DEBUG_Pos)
#define	WWDT_WWDTCON_CMPDAT_Pos		(16)
#define WWDT_WWDTCON_CMPDAT_Msk		(0x3fUL<<WWDT_WWDTCON_CMPDAT_Pos)
#define	WWDT_WWDTCON_PSCSEL_Pos		(4)
#define WWDT_WWDTCON_PSCSEL_Msk		(0xfUL<<WWDT_WWDTCON_PSCSEL_Pos)
#define	WWDT_WWDTCON_WWDTRF_Pos		(2)
#define WWDT_WWDTCON_WWDTRF_Msk		(0x1UL<<WWDT_WWDTCON_WWDTRF_Pos)
#define	WWDT_WWDTCON_WWDTIEN_Pos	(1)
#define WWDT_WWDTCON_WWDTIEN_Msk	(0x1UL<<WWDT_WWDTCON_WWDTIEN_Pos)
#define	WWDT_WWDTCON_WWDTEN_Pos		(0)
#define WWDT_WWDTCON_WWDTEN_Msk		(0x1UL<<WWDT_WWDTCON_WWDTEN_Pos)
/*------WWDTRIS-----------------------------------------------------------*/
#define	WWDT_WWDTRIS_WWDTRIS_Pos	(0)
#define WWDT_WWDTRIS_WWDTRIS_Msk	(0x1UL<<WWDT_WWDTRIS_WWDTRIS_Pos)
/*------WWDTMIS-----------------------------------------------------------*/
#define	WWDT_WWDTMIS_WWDTMIS_Pos	(0)
#define WWDT_WWDTMIS_WWDTMIS_Msk	(0x1UL<<WWDT_WWDTMIS_WWDTMIS_Pos)
/*------WWDTICLR----------------------------------------------------------*/
#define	WWDT_WWDTICLR_WWDTICLR_Pos	(0)
#define WWDT_WWDTICLR_WWDTICLR_Msk	(0x1UL<<WWDT_WWDTICLR_WWDTICLR_Pos)

/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief CRC Decription (CRC)
  */

typedef struct {                                /*!< (@ 0x4A000000) CRC Structure                                              */
  __IOM uint32_t  CRCIN;                        /*!< (@ 0x00000000) CRCIN Description                                          */
  __IOM uint32_t  CRCD;                         /*!< (@ 0x00000004) CRCD Description                                           */
} CRC_Type;                                     /*!< Size = 8 (0x8)                                                            */



/* =========================================================================================================================== */
/* ================                                           HWDIV                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief HWDIV Decription (HWDIV)
  */

typedef struct {                                /*!< (@ 0x55000000) HWDIV Structure                                            */
  __IOM uint32_t  CON;                          /*!< (@ 0x00000000) CON Description                                            */
  __IOM uint32_t  DIVD;                         /*!< (@ 0x00000004) DIVD Description                                           */
  __IOM uint32_t  DIVS;                         /*!< (@ 0x00000008) DIVS Description                                           */
  __IM  uint32_t  DIVQ;                         /*!< (@ 0x0000000C) DIVQ Description                                           */
  __IM  uint32_t  DIVR;                         /*!< (@ 0x00000010) DIVR Description                                           */
} HWDIV_Type;                                   /*!< Size = 20 (0x14)                                                          */

/*------HDIV-------------------------------------------------------------*/
#define	HDIV_CON_READY_Pos			(3)
#define HDIV_CON_READY_Msk			(0x1UL<<HDIV_CON_READY_Pos)
#define	HDIV_CON_DIVBY0_Pos			(2)
#define HDIV_CON_DIVBY0_Msk			(0x1UL<<HDIV_CON_DIVBY0_Pos)
#define	HDIV_CON_SIGN_Pos			(1)
#define HDIV_CON_SIGN_Msk			(0x1UL<<HDIV_CON_SIGN_Pos)

/* =========================================================================================================================== */
/* ================                                          TIMER0                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief TIMER0 Decription (TIMER0)
  */

typedef struct {                                /*!< (@ 0x46800000) TIMER0 Structure                                           */
  __IOM uint32_t  TIMER0CON;                    /*!< (@ 0x00000000) TIMER0CON Description                                      */
  __IOM uint32_t  TIMER0LOAD;                   /*!< (@ 0x00000004) TIMER0LOAD Description                                     */
  __IM  uint32_t  TIMER0VAL;                    /*!< (@ 0x00000008) TIMER0VAL Description                                      */
  __IM  uint32_t  TIMER0RIS;                    /*!< (@ 0x0000000C) TIMER0RIS Description                                      */
  __IM  uint32_t  TIMER0MIS;                    /*!< (@ 0x00000010) TIMER0MIS Description                                      */
  __OM  uint32_t  TIMER0ICLR;                   /*!< (@ 0x00000014) TIMER0ICLR Description                                     */
  __IOM uint32_t  TIMER0BGLOAD;                 /*!< (@ 0x00000018) TIMER0BGLOAD Description                                   */
} TIMER0_Type;                                  /*!< Size = 28 (0x1c)                                                          */

/*------CON---------------------------------------------------------------*/
#define	TMR_CON_TMREN_Pos			(7)
#define TMR_CON_TMREN_Msk			(0x1UL<<TMR_CON_TMREN_Pos)
#define	TMR_CON_TMRMS_Pos			(6)
#define TMR_CON_TMRMS_Msk			(0x1UL<<TMR_CON_TMRMS_Pos)
#define	TMR_CON_TMRIE_Pos			(5)
#define TMR_CON_TMRIE_Msk			(0x1UL<<TMR_CON_TMRIE_Pos)
#define	TMR_CON_TMRPRE_Pos			(2)
#define TMR_CON_TMRPRE_Msk			(0x3UL<<TMR_CON_TMRPRE_Pos)
#define	TMR_CON_TMRSZ_Pos			(1)
#define TMR_CON_TMRSZ_Msk			(0x1UL<<TMR_CON_TMRSZ_Pos)
#define	TMR_CON_TMROS_Pos			(0)
#define TMR_CON_TMROS_Msk			(0x1UL<<TMR_CON_TMROS_Pos)
/*------RIS---------------------------------------------------------------*/
#define	TMR_RIS_RIS_Pos				(0)
#define TMR_RIS_RIS_Msk				(0x1UL<<TMR_RIS_RIS_Pos)
/*------MIS---------------------------------------------------------------*/
#define	TMR_MIS_MIS_Pos				(0)
#define TMR_MIS_MIS_Msk				(0x1UL<<TMR_MIS_MIS_Pos)
/*------ICLR--------------------------------------------------------------*/
#define	TMR_ICLR_ICLR_Pos			(0)
#define TMR_ICLR_ICLR_Msk			(0x1UL<<TMR_ICLR_ICLR_Pos)

/* =========================================================================================================================== */
/* ================                                            CCP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief CCP Decription (CCP)
  */

typedef struct {                                /*!< (@ 0x42800000) CCP Structure                                              */
  __IOM uint32_t  CON0;                      /*!< (@ 0x00000000) CCPCON0 Description                                        */
  __IOM uint32_t  LOAD0;                     /*!< (@ 0x00000004) CCPLOAD0 Description                                       */
  __IOM uint32_t  D0A;                       /*!< (@ 0x00000008) CCPD0A Description                                         */
  __IOM uint32_t  D0B;                       /*!< (@ 0x0000000C) CCPD0B Description                                         */
  __IOM uint32_t  CON1;                      /*!< (@ 0x00000010) CCPCON1 Description                                        */
  __IOM uint32_t  LOAD1;                     /*!< (@ 0x00000014) CCPLOAD1 Description                                       */
  __IOM uint32_t  D1A;                       /*!< (@ 0x00000018) CCPD1A Description                                         */
  __IOM uint32_t  D1B;                       /*!< (@ 0x0000001C) CCPD1B Description                                         */
  __IM  uint32_t  RESERVED[8];
  __IOM uint32_t  IMSC;                      /*!< (@ 0x00000040) CCPIMSC Description                                        */
  __IM  uint32_t  RIS;                       /*!< (@ 0x00000044) CCPRIS Description                                         */
  __IM  uint32_t  MIS;                       /*!< (@ 0x00000048) CCPMIS Description                                         */
  __OM  uint32_t  ICLR;                      /*!< (@ 0x0000004C) CCPICLR Description                                        */
  __IOM uint32_t  RUN;                       /*!< (@ 0x00000050) CCPRUN Description                                         */
  __IOM uint32_t  LOCK;                      /*!< (@ 0x00000054) CCPLOCK Description                                        */
  __IOM uint32_t  CAPCON;                       /*!< (@ 0x00000058) CAPCON Description                                         */
  __IOM uint32_t  CAPCHS;                       /*!< (@ 0x0000005C) CAPCHS Description                                         */
	__IOM uint32_t  CAPnDAT[4];
  //__IOM uint32_t  CAP0DAT0;                     /*!< (@ 0x00000060) CAP0DAT0 Description                                       */
  //__IOM uint32_t  CAP1DAT0;                     /*!< (@ 0x00000064) CAP1DAT0 Description                                       */
  //__IOM uint32_t  CAP2DAT0;                     /*!< (@ 0x00000068) CAP2DAT0 Description                                       */
 // __IOM uint32_t  CAP3DAT0;                     /*!< (@ 0x0000006C) CAP3DAT0 Description                                       */
} CCP_Type;                                     /*!< Size = 112 (0x70)                                                         */

/*------CCPCON0-------------------------------------------------------------*/
#define	CCP_CCPCON0_CCP0EN_Pos		(6)
#define CCP_CCPCON0_CCP0EN_Msk		(0x1UL<<CCP_CCPCON0_CCP0EN_Pos)
#define	CCP_CCPCON0_CCP0PS_Pos		(4)
#define CCP_CCPCON0_CCP0PS_Msk		(0x3UL<<CCP_CCPCON0_CCP0PS_Pos)
#define	CCP_CCPCON0_CCP0MS_Pos		(3)
#define CCP_CCPCON0_CCP0MS_Msk		(0x1UL<<CCP_CCPCON0_CCP0MS_Pos)
#define	CCP_CCPCON0_CCP0CM0CS_Pos	(2)
#define CCP_CCPCON0_CCP0CM0CS_Msk	(0x1UL<<CCP_CCPCON0_CCP0CM0CS_Pos)
#define	CCP_CCPCON0_CCP0CM0ES_Pos	(0)
#define CCP_CCPCON0_CCP0CM0ES_Msk	(0x3UL<<CCP_CCPCON0_CCP0CM0ES_Pos)
/*------CCPLOAD0------------------------------------------------------------*/
#define	CCP_CCPLOAD0_RELOAD_Pos		(16)
#define CCP_CCPLOAD0_RELOAD_Msk		(0x1UL<<CCP_CCPLOAD0_RELOAD_Pos)
#define	CCP_CCPLOAD0_LOAD_Pos		(0)
#define CCP_CCPLOAD0_LOAD_Msk		(0xffffUL<<CCP_CCPLOAD0_LOAD_Pos)
/*------CCPD0A--------------------------------------------------------------*/
#define	CCP_CCPD0A_PWM0AOP_Pos		(16)
#define CCP_CCPD0A_PWM0AOP_Msk		(0x1UL<<CCP_CCPD0A_PWM0AOP_Pos)
#define	CCP_CCPD0A_DATA_Pos			(0)
#define CCP_CCPD0A_DATA_Msk			(0xffffUL<<CCP_CCPD0A_DATA_Pos)
/*------CCPD0B--------------------------------------------------------------*/
#define	CCP_CCPD0B_PWM0BOP_Pos		(16)
#define CCP_CCPD0B_PWM0BOP_Msk		(0x1UL<<CCP_CCPD0B_PWM0BOP_Pos)
#define	CCP_CCPD0B_DATA_Pos			(0)
#define CCP_CCPD0B_DATA_Msk			(0xffffUL<<CCP_CCPD0B_DATA_Pos)

/*------CCPCON1-------------------------------------------------------------*/
#define	CCP_CCPCON1_CCP1EN_Pos		(6)
#define CCP_CCPCON1_CCP1EN_Msk		(0x1UL<<CCP_CCPCON1_CCP1EN_Pos)
#define	CCP_CCPCON1_CCP1PS_Pos		(4)
#define CCP_CCPCON1_CCP1PS_Msk		(0x3UL<<CCP_CCPCON1_CCP1PS_Pos)
#define	CCP_CCPCON1_CCP1MS_Pos		(3)
#define CCP_CCPCON1_CCP1MS_Msk		(0x1UL<<CCP_CCPCON1_CCP1MS_Pos)
#define	CCP_CCPCON1_CCP1CM0CS_Pos	(2)
#define CCP_CCPCON1_CCP1CM0CS_Msk	(0x1UL<<CCP_CCPCON1_CCP1CM0CS_Pos)
#define	CCP_CCPCON1_CCP1CM0ES_Pos	(0)
#define CCP_CCPCON1_CCP1CM0ES_Msk	(0x3UL<<CCP_CCPCON1_CCP1CM0ES_Pos)
/*------CCPLOAD1------------------------------------------------------------*/
#define	CCP_CCPLOAD1_RELOAD_Pos		(16)
#define CCP_CCPLOAD1_RELOAD_Msk		(0x1UL<<CCP_CCPLOAD1_RELOAD_Pos)
#define	CCP_CCPLOAD1_LOAD_Pos		(0)
#define CCP_CCPLOAD1_LOAD_Msk		(0xffffUL<<CCP_CCPLOAD1_LOAD_Pos)
/*------CCPD1A--------------------------------------------------------------*/
#define	CCP_CCPD1A_PWM1AOP_Pos		(16)
#define CCP_CCPD1A_PWM1AOP_Msk		(0x1UL<<CCP_CCPD1A_PWM1AOP_Pos)
#define	CCP_CCPD1A_DATA_Pos			(0)
#define CCP_CCPD1A_DATA_Msk			(0xffffUL<<CCP_CCPD1A_DATA_Pos)
/*------CCPD1B--------------------------------------------------------------*/
#define	CCP_CCPD1B_PWM1BOP_Pos		(16)
#define CCP_CCPD1B_PWM1BOP_Msk		(0x1UL<<CCP_CCPD1B_PWM1BOP_Pos)
#define	CCP_CCPD1B_DATA_Pos			(0)
#define CCP_CCPD1B_DATA_Msk			(0xffffUL<<CCP_CCPD1B_DATA_Pos)
/*------CCPIMSC--------------------------------------------------------------*/
#define	CCP_CCPIMSC_CAP3IMSC_Pos	(11)
#define CCP_CCPIMSC_CAP3IMSC_Msk	(0x1UL<<CCP_CCPIMSC_CAP3IMSC_Pos)
#define	CCP_CCPIMSC_CAP2IMSC_Pos	(10)
#define CCP_CCPIMSC_CAP2IMSC_Msk	(0x1UL<<CCP_CCPIMSC_CAP2IMSC_Pos)
#define	CCP_CCPIMSC_CAP1IMSC_Pos	(9)
#define CCP_CCPIMSC_CAP1IMSC_Msk	(0x1UL<<CCP_CCPIMSC_CAP1IMSC_Pos)
#define	CCP_CCPIMSC_CAP0IMSC_Pos	(8)
#define CCP_CCPIMSC_CAP0IMSC_Msk	(0x1UL<<CCP_CCPIMSC_CAP0IMSC_Pos)
#define	CCP_CCPIMSC_PWMIMSC5_Pos	(5)
#define CCP_CCPIMSC_PWMIMSC5_Msk	(0x1UL<<CCP_CCPIMSC_PWMIMSC5_Pos)
#define	CCP_CCPIMSC_PWMIMSC4_Pos	(4)
#define CCP_CCPIMSC_PWMIMSC4_Msk	(0x1UL<<CCP_CCPIMSC_PWMIMSC4_Pos)
#define	CCP_CCPIMSC_PWMIMSC1_Pos	(1)
#define CCP_CCPIMSC_PWMIMSC1_Msk	(0x1UL<<CCP_CCPIMSC_PWMIMSC1_Pos)
#define	CCP_CCPIMSC_PWMIMSC0_Pos	(0)
#define CCP_CCPIMSC_PWMIMSC0_Msk	(0x1UL<<CCP_CCPIMSC_PWMIMSC0_Pos)

/*------CCPRIS---------------------------------------------------------------*/
#define	CCP_CCPRIS_CAP3IRIS_Pos		(11)
#define CCP_CCPRIS_CAP3IRIS_Msk		(0x1UL<<CCP_CCPRIS_CAP3IRIS_Pos)
#define	CCP_CCPRIS_CAP2IRIS_Pos		(10)
#define CCP_CCPRIS_CAP2IRIS_Msk		(0x1UL<<CCP_CCPRIS_CAP2IRIS_Pos)
#define	CCP_CCPRIS_CAP1IRIS_Pos		(9)
#define CCP_CCPRIS_CAP1IRIS_Msk		(0x1UL<<CCP_CCPRIS_CAP1IRIS_Pos)
#define	CCP_CCPRIS_CAP0IRIS_Pos		(8)
#define CCP_CCPRIS_CAP0IRIS_Msk		(0x1UL<<CCP_CCPRIS_CAP0IRIS_Pos)
#define	CCP_CCPRIS_PWMRIS5_Pos		(5)
#define CCP_CCPRIS_PWMRIS5_Msk		(0x1UL<<CCP_CCPRIS_PWMRIS5_Pos)
#define	CCP_CCPRIS_PWMRIS4_Pos		(4)
#define CCP_CCPRIS_PWMRIS4_Msk		(0x1UL<<CCP_CCPRIS_PWMRIS4_Pos)
#define	CCP_CCPRIS_PWMRIS1_Pos		(1)
#define CCP_CCPRIS_PWMRIS1_Msk		(0x1UL<<CCP_CCPRIS_PWMRIS1_Pos)
#define	CCP_CCPRIS_PWMRIS0_Pos		(0)
#define CCP_CCPRIS_PWMRIS0_Msk		(0x1UL<<CCP_CCPRIS_PWMRIS0_Pos)
/*------CCPMIS---------------------------------------------------------------*/
#define	CCP_CCPMIS_CAP3IMIS_Pos		(11)
#define CCP_CCPMIS_CAP3IMIS_Msk		(0x1UL<<CCP_CCPMIS_CAP3IMIS_Pos)
#define	CCP_CCPMIS_CAP2IMIS_Pos		(10)
#define CCP_CCPMIS_CAP2IMIS_Msk		(0x1UL<<CCP_CCPMIS_CAP2IMIS_Pos)
#define	CCP_CCPMIS_CAP1IMIS_Pos		(9)
#define CCP_CCPMIS_CAP1IMIS_Msk		(0x1UL<<CCP_CCPMIS_CAP1IMIS_Pos)
#define	CCP_CCPMIS_CAP0IMIS_Pos		(8)
#define CCP_CCPMIS_CAP0IMIS_Msk		(0x1UL<<CCP_CCPMIS_CAP0IMIS_Pos)
#define	CCP_CCPMIS_PWMMIS5_Pos		(5)
#define CCP_CCPMIS_PWMMIS5_Msk		(0x1UL<<CCP_CCPMIS_PWMMIS5_Pos)
#define	CCP_CCPMIS_PWMMIS4_Pos		(4)
#define CCP_CCPMIS_PWMMIS4_Msk		(0x1UL<<CCP_CCPMIS_PWMMIS4_Pos)
#define	CCP_CCPMIS_PWMMIS1_Pos		(1)
#define CCP_CCPMIS_PWMMIS1_Msk		(0x1UL<<CCP_CCPMIS_PWMMIS1_Pos)
#define	CCP_CCPMIS_PWMMIS0_Pos		(0)
#define CCP_CCPMIS_PWMMIS0_Msk		(0x1UL<<CCP_CCPMIS_PWMMIS0_Pos)

/*------CCPICLR-------------------------------------------------------------*/
#define	CCP_CCPICLR_CAP3ICLR_Pos	(11)
#define CCP_CCPICLR_CAP3ICLR_Msk	(0x1UL<<CCP_CCPICLR_CAP3ICLR_Pos)
#define	CCP_CCPICLR_CAP2ICLR_Pos	(10)
#define CCP_CCPICLR_CAP2ICLR_Msk	(0x1UL<<CCP_CCPICLR_CAP2ICLR_Pos)
#define	CCP_CCPICLR_CAP1ICLR_Pos	(9)
#define CCP_CCPICLR_CAP1ICLR_Msk	(0x1UL<<CCP_CCPICLR_CAP1ICLR_Pos)
#define	CCP_CCPICLR_CAP0ICLR_Pos	(8)
#define CCP_CCPICLR_CAP0ICLR_Msk	(0x1UL<<CCP_CCPICLR_CAP0ICLR_Pos)
#define	CCP_CCPICLR_PWMMICLR5_Pos	(5)
#define CCP_CCPICLR_PWMMICLR5_Msk	(0x1UL<<CCP_CCPICLR_PWMMICLR5_Pos)
#define	CCP_CCPICLR_PWMMICLR4_Pos	(4)
#define CCP_CCPICLR_PWMMICLR4_Msk	(0x1UL<<CCP_CCPICLR_PWMMICLR4_Pos)
#define	CCP_CCPICLR_PWMMICLR1_Pos	(1)
#define CCP_CCPICLR_PWMMICLR1_Msk	(0x1UL<<CCP_CCPICLR_PWMMICLR1_Pos)
#define	CCP_CCPICLR_PWMMICLR0_Pos	(0)
#define CCP_CCPICLR_PWMMICLR0_Msk	(0x1UL<<CCP_CCPICLR_PWMMICLR0_Pos)
/*------CCPRUN-------------------------------------------------------------*/
#define	CCP_CCPRUN_CCPRUN1_Pos		(1)
#define CCP_CCPRUN_CCPRUN1_Msk		(0x1UL<<CCP_CCPRUN_CCPRUN1_Pos)
#define	CCP_CCPRUN_CCPRUN0_Pos		(0)
#define CCP_CCPRUN_CCPRUN0_Msk		(0x1UL<<CCP_CCPRUN_CCPRUN0_Pos)
/*------CAPCON-------------------------------------------------------------*/
#define	CCP_CAPCON_CAPEN_Pos		(12)
#define CCP_CAPCON_CAPEN_Msk		(0x1UL<<CCP_CAPCON_CAPEN_Pos)
#define	CCP_CAPCON_CAP3RLEN_Pos		(11)
#define CCP_CAPCON_CAP3RLEN_Msk		(0x1UL<<CCP_CAPCON_CAP3RLEN_Pos)
#define	CCP_CAPCON_CAP2RLEN_Pos		(10)
#define CCP_CAPCON_CAP2RLEN_Msk		(0x1UL<<CCP_CAPCON_CAP2RLEN_Pos)
#define	CCP_CAPCON_CAP1RLEN_Pos		(9)
#define CCP_CAPCON_CAP1RLEN_Msk		(0x1UL<<CCP_CAPCON_CAP1RLEN_Pos)
#define	CCP_CAPCON_CAP0RLEN_Pos		(8)
#define CCP_CAPCON_CAP0RLEN_Msk		(0x1UL<<CCP_CAPCON_CAP0RLEN_Pos)
#define	CCP_CAPCON_CAP3ES_Pos		(5)
#define CCP_CAPCON_CAP3ES_Msk		(0x7UL<<CCP_CAPCON_CAP3ES_Pos)
#define	CCP_CAPCON_CAP2ES_Pos		(4)
#define CCP_CAPCON_CAP2ES_Msk		(0x3UL<<CCP_CAPCON_CAP2ES_Pos)
#define	CCP_CAPCON_CAP1ES_Pos		(2)
#define CCP_CAPCON_CAP1ES_Msk		(0x3UL<<CCP_CAPCON_CAP1ES_Pos)
#define	CCP_CAPCON_CAP0ES_Pos		(0)
#define CCP_CAPCON_CAP0ES_Msk		(0x3UL<<CCP_CAPCON_CAP0ES_Pos)
/*------CAPCHS-------------------------------------------------------------*/
#define	CCP_CAPCHS_ECAPS_Pos		(16)
#define CCP_CAPCHS_ECAPS_Msk		(0x1UL<<CCP_CAPCHS_ECAPS_Pos)
#define	CCP_CAPCHS_CAP3CHS_Pos		(12)
#define CCP_CAPCHS_CAP3CHS_Msk		(0xfUL<<CCP_CAPCHS_CAP3CHS_Pos)
#define	CCP_CAPCHS_CAP2CHS_Pos		(8)
#define CCP_CAPCHS_CAP2CHS_Msk		(0xfUL<<CCP_CAPCHS_CAP2CHS_Pos)
#define	CCP_CAPCHS_CAP1CHS_Pos		(4)
#define CCP_CAPCHS_CAP1CHS_Msk		(0xfUL<<CCP_CAPCHS_CAP1CHS_Pos)
#define	CCP_CAPCHS_CAP0CHS_Pos		(0)
#define CCP_CAPCHS_CAP0CHS_Msk		(0xfUL<<CCP_CAPCHS_CAP0CHS_Pos)
/*------CAP0DAT-------------------------------------------------------------*/
#define	CCP_CAP0DAT_CAP_Pos			(16)
#define CCP_CAP0DAT_CAP_Msk			(0xffffUL<<CCP_CAP0DAT_CAP_Pos)
#define	CCP_CAP0DAT_DAT_Pos			(0)
#define CCP_CAP0DAT_DAT_Msk			(0xffffUL<<CCP_CAP0DAT_DAT_Pos)
/*------CAP1DAT-------------------------------------------------------------*/
#define	CCP_CAP1DAT_CAP_Pos			(16)
#define CCP_CAP1DAT_CAP_Msk			(0xffffUL<<CCP_CAP1DAT_CAP_Pos)
#define	CCP_CAP1DAT_DAT_Pos			(0)
#define CCP_CAP1DAT_DAT_Msk			(0xffffUL<<CCP_CAP1DAT_DAT_Pos)
/*------CAP2DAT-------------------------------------------------------------*/
#define	CCP_CAP2DAT_CAP_Pos			(16)
#define CCP_CAP2DAT_CAP_Msk			(0xffffUL<<CCP_CAP2DAT_CAP_Pos)
#define	CCP_CAP2DAT_DAT_Pos			(0)
#define CCP_CAP2DAT_DAT_Msk			(0xffffUL<<CCP_CAP2DAT_DAT_Pos)
/*------CAP3DAT-------------------------------------------------------------*/
#define	CCP_CAP3DAT_CAP_Pos			(16)
#define CCP_CAP3DAT_CAP_Msk			(0xffffUL<<CCP_CAP3DAT_CAP_Pos)
#define	CCP_CAP3DAT_DAT_Pos			(0)
#define CCP_CAP3DAT_DAT_Msk			(0xffffUL<<CCP_CAP3DAT_DAT_Pos)

/* =========================================================================================================================== */
/* ================                                           EPWM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief EPWM Decription (EPWM)
  */

typedef struct {                                /*!< (@ 0x4A800000) EPWM Structure                                             */
  __IOM uint32_t  CLKPSC;                       /*!< (@ 0x00000000) CLKPSC Description                                         */
  __IOM uint32_t  CLKDIV;                       /*!< (@ 0x00000004) CLKDIV Description                                         */
  __IOM uint32_t  CON;                          /*!< (@ 0x00000008) CON Description                                            */
  __IOM uint32_t  CON2;                         /*!< (@ 0x0000000C) CON2 Description                                           */
  __IOM uint32_t  CON3;                         /*!< (@ 0x00000010) CON3 Description                                           */
  __IOM uint32_t  PERIOD[6];                      /*!< (@ 0x00000014) PERIOD0 Description                                        */
  __IOM uint32_t  CMPDAT[6];                      /*!< (@ 0x0000002C) CMPDAT0 Description                                        */
  __IOM uint32_t  POREMAP;                      /*!< (@ 0x00000044) POREMAP Description                                        */
  __IOM uint32_t  POEN;                         /*!< (@ 0x00000048) POEN Description                                           */
  __IOM uint32_t  BRKCTL;                       /*!< (@ 0x0000004C) BRKCTL Description                                         */
  __IOM uint32_t  DTCTL;                        /*!< (@ 0x00000050) DTCTL Description                                          */
  __IOM uint32_t  MASK;                         /*!< (@ 0x00000054) MASK Description                                           */
  __IOM uint32_t  MASKNXT;                      /*!< (@ 0x00000058) MASKNXT Description                                        */
  __IOM uint32_t  CMPTGD[2];                      /*!< (@ 0x0000005C) CMPTGD0 Description                                        */
  __IOM uint32_t  IMSC;                         /*!< (@ 0x00000064) IMSC Description                                           */
  __IM  uint32_t  RIS;                          /*!< (@ 0x00000068) RIS Description                                            */
  __IM  uint32_t  MIS;                          /*!< (@ 0x0000006C) MIS Description                                            */
  __OM  uint32_t  ICLR;                         /*!< (@ 0x00000070) ICLR Description                                           */
  __IOM uint32_t  IFA;                          /*!< (@ 0x00000074) IFA Description                                            */
  __IOM uint32_t  LOCK;                         /*!< (@ 0x00000078) LOCK Description                                           */
} EPWM_Type;                                    /*!< Size = 124 (0x7c)                                                         */

/*------CLKPSC--------------------------------------------------------------*/
#define	EPWM_CLKPSC_CLKPSC45_Pos		(16)
#define EPWM_CLKPSC_CLKPSC45_Msk		(0xffUL<<EPWM_CLKPSC_CLKPSC45_Pos)
#define	EPWM_CLKPSC_CLKPSC23_Pos		(8)
#define EPWM_CLKPSC_CLKPSC23_Msk		(0xffUL<<EPWM_CLKPSC_CLKPSC23_Pos)
#define	EPWM_CLKPSC_CLKPSC01_Pos		(0)
#define EPWM_CLKPSC_CLKPSC01_Msk		(0xffUL<<EPWM_CLKPSC_CLKPSC01_Pos)
/*------CLKDIV--------------------------------------------------------------*/
#define	EPWM_CLKDIV_CLKDIV5_Pos			(20)
#define EPWM_CLKDIV_CLKDIV5_Msk			(0x7UL<<EPWM_CLKDIV_CLKDIV5_Pos)
#define	EPWM_CLKDIV_CLKDIV4_Pos			(16)
#define EPWM_CLKDIV_CLKDIV4_Msk			(0x7UL<<EPWM_CLKDIV_CLKDIV4_Pos)
#define	EPWM_CLKDIV_CLKDIV3_Pos			(12)
#define EPWM_CLKDIV_CLKDIV3_Msk			(0x7UL<<EPWM_CLKDIV_CLKDIV3_Pos)
#define	EPWM_CLKDIV_CLKDIV2_Pos			(8)
#define EPWM_CLKDIV_CLKDIV2_Msk			(0x7UL<<EPWM_CLKDIV_CLKDIV2_Pos)
#define	EPWM_CLKDIV_CLKDIV1_Pos			(4)
#define EPWM_CLKDIV_CLKDIV1_Msk			(0x7UL<<EPWM_CLKDIV_CLKDIV1_Pos)
#define	EPWM_CLKDIV_CLKDIV0_Pos			(0)
#define EPWM_CLKDIV_CLKDIV0_Msk			(0x7UL<<EPWM_CLKDIV_CLKDIV0_Pos)
/*------CON--------------------------------------------------------------*/
#define	EPWM_CON_HALTMS_Pos				(26)
#define EPWM_CON_HALTMS_Msk				(0x1UL<<EPWM_CON_HALTMS_Pos)
#define	EPWM_CON_MODE_Pos				(24)
#define EPWM_CON_MODE_Msk				(0x3UL<<EPWM_CON_MODE_Pos)
#define	EPWM_CON_GROUNPEN_Pos			(23)
#define EPWM_CON_GROUNPEN_Msk			(0x1UL<<EPWM_CON_GROUNPEN_Pos)
#define	EPWM_CON_ASYMEN_Pos				(22)
#define EPWM_CON_ASYMEN_Msk				(0x1UL<<EPWM_CON_ASYMEN_Pos)
#define	EPWM_CON_CNTTYPE_Pos			(21)
#define EPWM_CON_CNTTYPE_Msk			(0x1UL<<EPWM_CON_CNTTYPE_Pos)
#define	EPWM_CON_ENDT45_Pos				(18)
#define EPWM_CON_ENDT45_Msk				(0x1UL<<EPWM_CON_ENDT45_Pos)
#define	EPWM_CON_ENDT23_Pos				(17)
#define EPWM_CON_ENDT23_Msk				(0x1UL<<EPWM_CON_ENDT23_Pos)
#define	EPWM_CON_ENDT01_Pos				(16)
#define EPWM_CON_ENDT01_Msk				(0x1UL<<EPWM_CON_ENDT01_Pos)
#define	EPWM_CON_PINV5_Pos				(13)
#define EPWM_CON_PINV5_Msk				(0x1UL<<EPWM_CON_PINV5_Pos)
#define	EPWM_CON_PINV4_Pos				(12)
#define EPWM_CON_PINV4_Msk				(0x1UL<<EPWM_CON_PINV4_Pos)
#define	EPWM_CON_PINV3_Pos				(11)
#define EPWM_CON_PINV3_Msk				(0x1UL<<EPWM_CON_PINV3_Pos)
#define	EPWM_CON_PINV2_Pos				(10)
#define EPWM_CON_PINV2_Msk				(0x1UL<<EPWM_CON_PINV2_Pos)
#define	EPWM_CON_PINV1_Pos				(9)
#define EPWM_CON_PINV1_Msk				(0x1UL<<EPWM_CON_PINV1_Pos)
#define	EPWM_CON_PINV0_Pos				(8)
#define EPWM_CON_PINV0_Msk				(0x1UL<<EPWM_CON_PINV0_Pos)
#define	EPWM_CON_CNTMODE5_Pos			(5)
#define EPWM_CON_CNTMODE5_Msk			(0x1UL<<EPWM_CON_CNTMODE5_Pos)
#define	EPWM_CON_CNTMODE4_Pos			(4)
#define EPWM_CON_CNTMODE4_Msk			(0x1UL<<EPWM_CON_CNTMODE4_Pos)
#define	EPWM_CON_CNTMODE3_Pos			(3)
#define EPWM_CON_CNTMODE3_Msk			(0x1UL<<EPWM_CON_CNTMODE3_Pos)
#define	EPWM_CON_CNTMODE2_Pos			(2)
#define EPWM_CON_CNTMODE2_Msk			(0x1UL<<EPWM_CON_CNTMODE2_Pos)
#define	EPWM_CON_CNTMODE1_Pos			(1)
#define EPWM_CON_CNTMODE1_Msk			(0x1UL<<EPWM_CON_CNTMODE1_Pos)
#define	EPWM_CON_CNTMODE0_Pos			(0)
#define EPWM_CON_CNTMODE0_Msk			(0x1UL<<EPWM_CON_CNTMODE0_Pos)
/*------CON2--------------------------------------------------------------*/
#define	EPWM_CON2_CNTEN5_Pos			(5)
#define EPWM_CON2_CNTEN5_Msk			(0x1UL<<EPWM_CON2_CNTEN5_Pos)
#define	EPWM_CON2_CNTEN4_Pos			(4)
#define EPWM_CON2_CNTEN4_Msk			(0x1UL<<EPWM_CON2_CNTEN4_Pos)
#define	EPWM_CON2_CNTEN3_Pos			(3)
#define EPWM_CON2_CNTEN3_Msk			(0x1UL<<EPWM_CON2_CNTEN3_Pos)
#define	EPWM_CON2_CNTEN2_Pos			(2)
#define EPWM_CON2_CNTEN2_Msk			(0x1UL<<EPWM_CON2_CNTEN2_Pos)
#define	EPWM_CON2_CNTEN1_Pos			(1)
#define EPWM_CON2_CNTEN1_Msk			(0x1UL<<EPWM_CON2_CNTEN1_Pos)
#define	EPWM_CON2_CNTEN0_Pos			(0)
#define EPWM_CON2_CNTEN0_Msk			(0x1UL<<EPWM_CON2_CNTEN0_Pos)
/*------CON3--------------------------------------------------------------*/
#define	EPWM_CON3_LOADTYP5_Pos			(26)
#define EPWM_CON3_LOADTYP5_Msk			(0x3UL<<EPWM_CON3_LOADTYP5_Pos)
#define	EPWM_CON3_LOADTYP4_Pos			(24)
#define EPWM_CON3_LOADTYP4_Msk			(0x3UL<<EPWM_CON3_LOADTYP4_Pos)
#define	EPWM_CON3_LOADTYP3_Pos			(22)
#define EPWM_CON3_LOADTYP3_Msk			(0x3UL<<EPWM_CON3_LOADTYP3_Pos)
#define	EPWM_CON3_LOADTYP2_Pos			(20)
#define EPWM_CON3_LOADTYP2_Msk			(0x3UL<<EPWM_CON3_LOADTYP2_Pos)
#define	EPWM_CON3_LOADTYP1_Pos			(18)
#define EPWM_CON3_LOADTYP1_Msk			(0x3UL<<EPWM_CON3_LOADTYP1_Pos)
#define	EPWM_CON3_LOADTYP0_Pos			(16)
#define EPWM_CON3_LOADTYP0_Msk			(0x3UL<<EPWM_CON3_LOADTYP0_Pos)
#define	EPWM_CON3_LOADEN5_Pos			(13)
#define EPWM_CON3_LOADEN5_Msk			(0x1UL<<EPWM_CON3_LOADEN5_Pos)
#define	EPWM_CON3_LOADEN4_Pos			(12)
#define EPWM_CON3_LOADEN4_Msk			(0x3UL<<EPWM_CON3_LOADEN4_Pos)
#define	EPWM_CON3_LOADEN3_Pos			(11)
#define EPWM_CON3_LOADEN3_Msk			(0x1UL<<EPWM_CON3_LOADEN3_Pos)
#define	EPWM_CON3_LOADEN2_Pos			(10)
#define EPWM_CON3_LOADEN2_Msk			(0x1UL<<EPWM_CON3_LOADEN2_Pos)
#define	EPWM_CON3_LOADEN1_Pos			(9)
#define EPWM_CON3_LOADEN1_Msk			(0x1UL<<EPWM_CON3_LOADEN1_Pos)
#define	EPWM_CON3_LOADEN0_Pos			(8)
#define EPWM_CON3_LOADEN0_Msk			(0x1UL<<EPWM_CON3_LOADEN0_Pos)
#define	EPWM_CON3_CNTCLR5_Pos			(5)
#define EPWM_CON3_CNTCLR5_Msk			(0x1UL<<EPWM_CON3_CNTCLR5_Pos)
#define	EPWM_CON3_CNTCLR4_Pos			(4)
#define EPWM_CON3_CNTCLR4_Msk			(0x1UL<<EPWM_CON3_CNTCLR4_Pos)
#define	EPWM_CON3_CNTCLR3_Pos			(3)
#define EPWM_CON3_CNTCLR3_Msk			(0x1UL<<EPWM_CON3_CNTCLR3_Pos)
#define	EPWM_CON3_CNTCLR2_Pos			(2)
#define EPWM_CON3_CNTCLR2_Msk			(0x1UL<<EPWM_CON3_CNTCLR2_Pos)
#define	EPWM_CON3_CNTCLR1_Pos			(1)
#define EPWM_CON3_CNTCLR1_Msk			(0x1UL<<EPWM_CON3_CNTCLR1_Pos)
#define	EPWM_CON3_CNTCLR0_Pos			(0)
#define EPWM_CON3_CNTCLR0_Msk			(0x1UL<<EPWM_CON3_CNTCLR0_Pos)

/*------POEN------------------------------------------------------------*/
#define	EPWM_POEN_POEN5_Pos				(5)
#define EPWM_POEN_POEN5_Msk				(0x1UL<<EPWM_POEN_POEN5_Pos)
#define	EPWM_POEN_POEN4_Pos				(4)
#define EPWM_POEN_POEN4_Msk				(0x1UL<<EPWM_POEN_POEN4_Pos)
#define	EPWM_POEN_POEN3_Pos				(3)
#define EPWM_POEN_POEN3_Msk				(0x1UL<<EPWM_POEN_POEN3_Pos)
#define	EPWM_POEN_POEN2_Pos				(2)
#define EPWM_POEN_POEN2_Msk				(0x1UL<<EPWM_POEN_POEN2_Pos)
#define	EPWM_POEN_POEN1_Pos				(1)
#define EPWM_POEN_POEN1_Msk				(0x1UL<<EPWM_POEN_POEN1_Pos)
#define	EPWM_POEN_POEN0_Pos				(0)
#define EPWM_POEN_POEN0_Msk				(0x1UL<<EPWM_POEN_POEN0_Pos)
/*------POREMAP---------------------------------------------------------*/
#define	EPWM_POREMAP_PWMRMEN_Pos		(24)
#define EPWM_POREMAP_PWMRMEN_Msk		(0xffUL<<EPWM_POREMAP_PWMRMEN_Pos)
#define	EPWM_POREMAP_PWM5RM_Pos			(20)
#define EPWM_POREMAP_PWM5RM_Msk			(0x7UL<<EPWM_POREMAP_PWM5RM_Pos)
#define	EPWM_POREMAP_PWM4RM_Pos			(16)
#define EPWM_POREMAP_PWM4RM_Msk			(0x7UL<<EPWM_POREMAP_PWM4RM_Pos)
#define	EPWM_POREMAP_PWM3RM_Pos			(12)
#define EPWM_POREMAP_PWM3RM_Msk			(0x7UL<<EPWM_POREMAP_PWM3RM_Pos)
#define	EPWM_POREMAP_PWM2RM_Pos			(8)
#define EPWM_POREMAP_PWM2RM_Msk			(0x7UL<<EPWM_POREMAP_PWM2RM_Pos)
#define	EPWM_POREMAP_PWM1RM_Pos			(4)
#define EPWM_POREMAP_PWM1RM_Msk			(0x7UL<<EPWM_POREMAP_PWM1RM_Pos)
#define	EPWM_POREMAP_PWM0RM_Pos			(0)
#define EPWM_POREMAP_PWM0RM_Msk			(0x7UL<<EPWM_POREMAP_PWM0RM_Pos)
/*------BRKCTL---------------------------------------------------------*/
#define	EPWM_BRKCTL_BRKEN_Pos			(31)
#define EPWM_BRKCTL_BRKEN_Msk			(0x1UL<<EPWM_BRKCTL_BRKEN_Pos)
#define	EPWM_BRKCTL_ACMP1BKEN_Pos		(19)
#define EPWM_BRKCTL_ACMP1BKEN_Msk		(0x1UL<<EPWM_BRKCTL_ACMP1BKEN_Pos)
#define	EPWM_BRKCTL_ACMP0BKEN_Pos		(18)
#define EPWM_BRKCTL_ACMP0BKEN_Msk		(0x1UL<<EPWM_BRKCTL_ACMP0BKEN_Pos)
#define	EPWM_BRKCTL_ADCBPM0BKEN_Pos		(16)
#define EPWM_BRKCTL_ADCBPM0BKEN_Msk		(0x1UL<<EPWM_BRKCTL_ADCBPM0BKEN_Pos)
#define	EPWM_BRKCTL_SWBRK_Pos			(12)
#define EPWM_BRKCTL_SWBRK_Msk			(0x1UL<<EPWM_BRKCTL_SWBRK_Pos)
#define	EPWM_BRKCTL_EXTBRKEE_Pos		(11)
#define EPWM_BRKCTL_EXTBRKEE_Msk		(0x1UL<<EPWM_BRKCTL_EXTBRKEE_Pos)
#define	EPWM_BRKCTL_EXTBRKES_Pos		(10)
#define EPWM_BRKCTL_EXTBRKES_Msk		(0x1UL<<EPWM_BRKCTL_EXTBRKES_Pos)
#define	EPWM_BRKCTL_EXTBRKLE_Pos		(9)
#define EPWM_BRKCTL_EXTBRKLE_Msk		(0x1UL<<EPWM_BRKCTL_EXTBRKLE_Pos)
#define	EPWM_BRKCTL_EXTBRKLS_Pos		(8)
#define EPWM_BRKCTL_EXTBRKLS_Msk		(0x1UL<<EPWM_BRKCTL_EXTBRKLS_Pos)
#define	EPWM_BRKCTL_BRKODn_Pos			(0)
#define EPWM_BRKCTL_BRKODn_Msk			(0x3fUL<<EPWM_BRKCTL_BRKODn_Pos)
/*------DTCTL---------------------------------------------------------*/
#define	EPWM_DTCTL_DTI45_Pos			(20)
#define EPWM_DTCTL_DTI45_Msk			(0x3ffUL<<EPWM_DTCTL_DTI45_Pos)
#define	EPWM_DTCTL_DTI23_Pos			(10)
#define EPWM_DTCTL_DTI23_Msk			(0x3ffUL<<EPWM_DTCTL_DTI23_Pos)
#define	EPWM_DTCTL_DTI01_Pos			(0)
#define EPWM_DTCTL_DTI01_Msk			(0x3ffUL<<EPWM_DTCTL_DTI01_Pos)
/*------MASK---------------------------------------------------------*/
#define	EPWM_MASK_MASKEN5_Pos			(13)
#define EPWM_MASK_MASKEN5_Msk			(0x1UL<<EPWM_MASK_MASKEN5_Pos)
#define	EPWM_MASK_MASKEN4_Pos			(12)
#define EPWM_MASK_MASKEN4_Msk			(0x1UL<<EPWM_MASK_MASKEN4_Pos)
#define	EPWM_MASK_MASKEN3_Pos			(11)
#define EPWM_MASK_MASKEN3_Msk			(0x1UL<<EPWM_MASK_MASKEN3_Pos)
#define	EPWM_MASK_MASKEN2_Pos			(10)
#define EPWM_MASK_MASKEN2_Msk			(0x1UL<<EPWM_MASK_MASKEN2_Pos)
#define	EPWM_MASK_MASKEN1_Pos			(9)
#define EPWM_MASK_MASKEN1_Msk			(0x1UL<<EPWM_MASK_MASKEN1_Pos)
#define	EPWM_MASK_MASKEN0_Pos			(8)
#define EPWM_MASK_MASKEN0_Msk			(0x1UL<<EPWM_MASK_MASKEN0_Pos)
#define	EPWM_MASK_MASKD5_Pos			(5)
#define EPWM_MASK_MASKD5_Msk			(0x1UL<<EPWM_MASK_MASKD5_Pos)
#define	EPWM_MASK_MASKD4_Pos			(4)
#define EPWM_MASK_MASKD4_Msk			(0x1UL<<EPWM_MASK_MASKD4_Pos)
#define	EPWM_MASK_MASKD3_Pos			(3)
#define EPWM_MASK_MASKD3_Msk			(0x1UL<<EPWM_MASK_MASKD3_Pos)
#define	EPWM_MASK_MASKD2_Pos			(2)
#define EPWM_MASK_MASKD2_Msk			(0x1UL<<EPWM_MASK_MASKD2_Pos)
#define	EPWM_MASK_MASKD1_Pos			(1)
#define EPWM_MASK_MASKD1_Msk			(0x1UL<<EPWM_MASK_MASKD1_Pos)
#define	EPWM_MASK_MASKD0_Pos			(0)
#define EPWM_MASK_MASKD0_Msk			(0x1UL<<EPWM_MASK_MASKD0_Pos)
/*------MASKNXT------------------------------------------------------*/
#define	EPWM_MASKNXT_HALLEN_Pos			(24)
#define EPWM_MASKNXT_HALLEN_Msk			(0x1UL<<EPWM_MASKNXT_HALLEN_Pos)
#define	EPWM_MASKNXT_HALLCLR_Pos		(23)
#define EPWM_MASKNXT_HALLCLR_Msk		(0x1UL<<EPWM_MASKNXT_HALLCLR_Pos)
#define	EPWM_MASKNXT_HALLST_Pos			(20)
#define EPWM_MASKNXT_HALLST_Msk			(0x7UL<<EPWM_MASKNXT_HALLST_Pos)
#define	EPWM_MASKNXT_PMASKSEL_Pos		(16)
#define EPWM_MASKNXT_PMASKSEL_Msk		(0x7UL<<EPWM_MASKNXT_PMASKSEL_Pos)
#define	EPWM_MASKNXT_PMASKEN5_Pos		(13)
#define EPWM_MASKNXT_PMASKEN5_Msk		(0x1UL<<EPWM_MASKNXT_PMASKEN5_Pos)
#define	EPWM_MASKNXT_PMASKEN4_Pos		(12)
#define EPWM_MASKNXT_PMASKEN4_Msk		(0x1UL<<EPWM_MASKNXT_PMASKEN4_Pos)
#define	EPWM_MASKNXT_PMASKEN3_Pos		(11)
#define EPWM_MASKNXT_PMASKEN3_Msk		(0x1UL<<EPWM_MASKNXT_PMASKEN3_Pos)
#define	EPWM_MASKNXT_PMASKEN2_Pos		(10)
#define EPWM_MASKNXT_PMASKEN2_Msk		(0x1UL<<EPWM_MASKNXT_PMASKEN2_Pos)
#define	EPWM_MASKNXT_PMASKEN1_Pos		(9)
#define EPWM_MASKNXT_PMASKEN1_Msk		(0x1UL<<EPWM_MASKNXT_PMASKEN1_Pos)
#define	EPWM_MASKNXT_PMASKEN0_Pos		(8)
#define EPWM_MASKNXT_PMASKEN0_Msk		(0x1UL<<EPWM_MASKNXT_PMASKEN0_Pos)
#define	EPWM_MASKNXT_PMASKD5_Pos		(5)
#define EPWM_MASKNXT_PMASKD5_Msk		(0x1UL<<EPWM_MASKNXT_PMASKD5_Pos)
#define	EPWM_MASKNXT_PMASKD4_Pos		(4)
#define EPWM_MASKNXT_PMASKD4_Msk		(0x1UL<<EPWM_MASKNXT_PMASKD4_Pos)
#define	EPWM_MASKNXT_PMASKD3_Pos		(3)
#define EPWM_MASKNXT_PMASKD3_Msk		(0x1UL<<EPWM_MASKNXT_PMASKD3_Pos)
#define	EPWM_MASKNXT_PMASKD2_Pos		(2)
#define EPWM_MASKNXT_PMASKD2_Msk		(0x1UL<<EPWM_MASKNXT_PMASKD2_Pos)
#define	EPWM_MASKNXT_PMASKD1_Pos		(1)
#define EPWM_MASKNXT_PMASKD1_Msk		(0x1UL<<EPWM_MASKNXT_PMASKD1_Pos)
#define	EPWM_MASKNXT_PMASKD0_Pos		(0)
#define EPWM_MASKNXT_PMASKD0_Msk		(0x1UL<<EPWM_MASKNXT_PMASKD0_Pos)

/*------CMPTGD-------------------------------------------------------*/
#define	EPWM_CMPTGD_CMPTGDS_Pos			(19)
#define EPWM_CMPTGD_CMPTGDS_Msk			(0x1UL<<EPWM_CMPTGD_CMPTGDS_Pos)
#define	EPWM_CMPTGD_CMPPCHS_Pos			(16)
#define EPWM_CMPTGD_CMPPCHS_Msk			(0x7UL<<EPWM_CMPTGD_CMPPCHS_Pos)
#define	EPWM_CMPTGD_CMPTGD_Pos			(0)
#define EPWM_CMPTGD_CMPTGD_Msk			(0xffffUL<<EPWM_CMPTGD_CMPTGD_Pos)

/*------IMSC---------------------------------------------------------*/
#define	EPWM_IMSC_ENBRKIF_Pos			(31)
#define EPWM_IMSC_ENBRKIF_Msk			(0x1UL<<EPWM_IMSC_ENBRKIF_Pos)
#define	EPWM_IMSC_ENHALLIF_Pos			(30)
#define EPWM_IMSC_ENHALLIF_Msk			(0x1UL<<EPWM_IMSC_ENHALLIF_Pos)
#define	EPWM_IMSC_ENDIFn_Pos			(24)
#define EPWM_IMSC_ENDIFn_Msk			(0x3fUL<<EPWM_IMSC_ENDIFn_Pos)
#define	EPWM_IMSC_ENUIFn_Pos			(16)
#define EPWM_IMSC_ENUIFn_Msk			(0x3fUL<<EPWM_IMSC_ENUIFn_Pos)
#define	EPWM_IMSC_ENDC1IF_Pos			(15)
#define EPWM_IMSC_ENDC1IF_Msk			(0x1UL<<EPWM_IMSC_ENDC1IF_Pos)
#define	EPWM_IMSC_ENDC0IF_Pos			(14)
#define EPWM_IMSC_ENDC0IF_Msk			(0x1UL<<EPWM_IMSC_ENDC0IF_Pos)
#define	EPWM_IMSC_ENPIFn_Pos			(8)
#define EPWM_IMSC_ENPIFn_Msk			(0x3fUL<<EPWM_IMSC_ENPIFn_Pos)
#define	EPWM_IMSC_ENZIFn_Pos			(0)
#define EPWM_IMSC_ENZIFn_Msk			(0x3fUL<<EPWM_IMSC_ENZIFn_Pos)
/*------IRS----------------------------------------------------------*/
#define	EPWM_RIS_BRKIF_Pos				(31)
#define EPWM_RIS_BRKIF_Msk				(0x1UL<<EPWM_RIS_BRKIF_Pos)
#define	EPWM_RIS_HALLIF_Pos				(30)
#define EPWM_RIS_HALLIF_Msk				(0x1UL<<EPWM_RIS_HALLIF_Pos)
#define	EPWM_RIS_DIFn_Pos				(24)
#define EPWM_RIS_DIFn_Msk				(0x3fUL<<EPWM_RIS_DIFn_Pos)	
#define	EPWM_RIS_UIFn_Pos				(16)
#define EPWM_RIS_UIFn_Msk				(0x3fUL<<EPWM_RIS_UIFn_Pos)	
#define	EPWM_RIS_DC1IF_Pos				(15)
#define EPWM_RIS_DC1IF_Msk				(0x1UL<<EPWM_RIS_DC1IF_Pos)	
#define	EPWM_RIS_DC0IF_Pos				(14)
#define EPWM_RIS_DC0IF_Msk				(0x1UL<<EPWM_RIS_DC0IF_Pos)	
#define	EPWM_RIS_PIFn_Pos				(8)
#define EPWM_RIS_PIFn_Msk				(0x3fUL<<EPWM_RIS_PIFn_Pos)	
#define	EPWM_RIS_ZIFn_Pos				(0)
#define EPWM_RIS_ZIFn_Msk				(0x3fUL<<EPWM_RIS_ZIFn_Pos)
/*------MIS----------------------------------------------------------*/
#define	EPWM_MIS_BRKIF_Pos				(31)
#define EPWM_MIS_BRKIF_Msk				(0x1UL<<EPWM_MIS_BRKIF_Pos)
#define	EPWM_MIS_HALLIF_Pos				(30)
#define EPWM_MIS_HALLIF_Msk				(0x1UL<<EPWM_MIS_HALLIF_Pos)
#define	EPWM_MIS_DIFn_Pos				(24)
#define EPWM_MIS_DIFn_Msk				(0x3fUL<<EPWM_MIS_DIFn_Pos)	
#define	EPWM_MIS_UIFn_Pos				(16)
#define EPWM_MIS_UIFn_Msk				(0x3fUL<<EPWM_MIS_UIFn_Pos)	
#define	EPWM_MIS_DC1IF_Pos				(15)
#define EPWM_MIS_DC1IF_Msk				(0x1UL<<EPWM_MIS_DC1IF_Pos)	
#define	EPWM_MIS_DC0IF_Pos				(14)
#define EPWM_MIS_DC0IF_Msk				(0x1UL<<EPWM_MIS_DC0IF_Pos)	
#define	EPWM_MIS_PIFn_Pos				(8)
#define EPWM_MIS_PIFn_Msk				(0x3fUL<<EPWM_MIS_PIFn_Pos)	
#define	EPWM_MIS_ZIFn_Pos				(0)
#define EPWM_MIS_ZIFn_Msk				(0x3fUL<<EPWM_MIS_ZIFn_Pos)
/*------ICLR----------------------------------------------------------*/
#define	EPWM_ICLR_BRKIF_Pos				(31)
#define EPWM_ICLR_BRKIF_Msk				(0x1UL<<EPWM_ICLR_BRKIF_Pos)
#define	EPWM_ICLR_HALLIF_Pos			(30)
#define EPWM_ICLR_HALLIF_Msk			(0x1UL<<EPWM_ICLR_HALLIF_Pos)
#define	EPWM_ICLR_DIFn_Pos				(24)
#define EPWM_ICLR_DIFn_Msk				(0x3fUL<<EPWM_ICLR_DIFn_Pos)	
#define	EPWM_ICLR_UIFn_Pos				(16)
#define EPWM_ICLR_UIFn_Msk				(0x3fUL<<EPWM_ICLR_UIFn_Pos)	
#define	EPWM_ICLR_DC1IF_Pos				(15)
#define EPWM_ICLR_DC1IF_Msk				(0x1UL<<EPWM_ICLR_DC1IF_Pos)	
#define	EPWM_ICLR_DC0IF_Pos				(14)
#define EPWM_ICLR_DC0IF_Msk				(0x1UL<<EPWM_ICLR_DC0IF_Pos)	
#define	EPWM_ICLR_PIFn_Pos				(8)
#define EPWM_ICLR_PIFn_Msk				(0x3fUL<<EPWM_ICLR_PIFn_Pos)	
#define	EPWM_ICLR_ZIFn_Pos				(0)
#define EPWM_ICLR_ZIFn_Msk				(0x3fUL<<EPWM_ICLR_ZIFn_Pos)
/*------IFA----------------------------------------------------------*/
#define	EPWM_IFA_ZIFCMP_Pos				(4)
#define EPWM_IFA_ZIFCMP_Msk				(0xfUL<<EPWM_IFA_ZIFCMP_Pos)
#define	EPWM_IFA_ZIFAEN_Pos				(0)
#define EPWM_IFA_ZIFAEN_Msk				(0x1UL<<EPWM_IFA_ZIFAEN_Pos)

/* =========================================================================================================================== */
/* ================                                           UART0                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief UART0 Decription (UART0)
  */

typedef struct {                                /*!< (@ 0x44800000) UART0 Structure                                            */
  __IM  uint32_t  RBR;                     /*!< (@ 0x00000000) UART0RBR Description                                       */
  __OM  uint32_t  THR;                     /*!< (@ 0x00000004) UART0THR Description                                       */
  __IOM uint32_t  DLR;                     /*!< (@ 0x00000008) UART0DLR Description                                       */
  __IOM uint32_t  IER;                     /*!< (@ 0x0000000C) UART0IER Description                                       */
  __IM  uint32_t  IIR;                     /*!< (@ 0x00000010) UART0IIR Description                                       */
  __OM  uint32_t  FCR;                     /*!< (@ 0x00000014) UART0FCR Description                                       */
  __IOM uint32_t  LCR;                     /*!< (@ 0x00000018) UART0LCR Description                                       */
  __IOM uint32_t  MCR;                     /*!< (@ 0x0000001C) UART0MCR Description                                       */
  __IM  uint32_t  LSR;                     /*!< (@ 0x00000020) UART0LSR Description                                       */
  __IM  uint32_t  MSR;                     /*!< (@ 0x00000024) UART0MSR Description                                       */
  __IOM uint32_t  SCR;                     /*!< (@ 0x00000028) UART0SCR Description                                       */
  __IOM uint32_t  EFR;                     /*!< (@ 0x0000002C) UART0EFR Description                                       */
  __IOM uint32_t  XON1;                    /*!< (@ 0x00000030) UART0XON1 Description                                      */
  __IOM uint32_t  XON2;                    /*!< (@ 0x00000034) UART0XON2 Description                                      */
  __IOM uint32_t  XOFF1;                   /*!< (@ 0x00000038) UART0XOFF1 Description                                     */
  __IOM uint32_t  XOFF2;                   /*!< (@ 0x0000003C) UART0XOFF2 Description                                     */
} UART0_Type;                                   /*!< Size = 64 (0x40)                                                          */

/*------IER----------------------------------------------------------*/
#define	UART_IER_CTSIE_Pos				(7)
#define UART_IER_CTSIE_Msk				(0x1UL<<UART_IER_CTSIE_Pos)
#define	UART_IER_RTSIE_Pos				(6)
#define UART_IER_RTSIE_Msk				(0x1UL<<UART_IER_RTSIE_Pos)
#define	UART_IER_XOFIE_Pos				(5)
#define UART_IER_XOFIE_Msk				(0x1UL<<UART_IER_XOFIE_Pos)
#define	UART_IER_MDSIE_Pos				(3)
#define UART_IER_MDSIE_Msk				(0x1UL<<UART_IER_MDSIE_Pos)
#define	UART_IER_RLSIE_Pos				(2)
#define UART_IER_RLSIE_Msk				(0x1UL<<UART_IER_RLSIE_Pos)
#define	UART_IER_THREIE_Pos				(1)
#define UART_IER_THREIE_Msk				(0x1UL<<UART_IER_THREIE_Pos)
#define	UART_IER_RBREIE_Pos				(0)
#define UART_IER_RBREIE_Msk				(0x1UL<<UART_IER_RBREIE_Pos)

/*------IIR----------------------------------------------------------*/
#define	UART_IIR_INTHFC_Pos				(5)
#define UART_IIR_INTHFC_Msk				(0x1UL<<UART_IIR_INTHFC_Pos)
#define	UART_IIR_INTSFC_Pos				(4)
#define UART_IIR_INTSFC_Msk				(0x1UL<<UART_IIR_INTSFC_Pos)
#define	UART_IIR_INTID_Pos				(1)
#define UART_IIR_INTID_Msk				(0x7UL<<UART_IIR_INTID_Pos)
#define	UART_IIR_INTSTATUS_Pos			(0)
#define UART_IIR_INTSTATUS_Msk			(0x1UL<<UART_IIR_INTSTATUS_Pos)
/*------FCR----------------------------------------------------------*/
#define	UART_FCR_RXTL_Pos				(6)
#define UART_FCR_RXTL_Msk				(0x3UL<<UART_FCR_RXTL_Pos)
#define	UART_FCR_TXTL_Pos				(4)
#define UART_FCR_TXTL_Msk				(0x3UL<<UART_FCR_TXTL_Pos)
#define	UART_FCR_TXFIFORST_Pos			(2)
#define UART_FCR_TXFIFORST_Msk			(0x1UL<<UART_FCR_TXFIFORST_Pos)
#define	UART_FCR_RXFIFORST_Pos			(1)
#define UART_FCR_RXFIFORST_Msk			(0x1UL<<UART_FCR_RXFIFORST_Pos)
#define	UART_FCR_FIFOEN_Pos				(0)
#define UART_FCR_FIFOEN_Msk				(0x1UL<<UART_FCR_FIFOEN_Pos)

/*------LCR----------------------------------------------------------*/
#define	UART_LCR_BCON_Pos				(6)
#define UART_LCR_BCON_Msk				(0x1UL<<UART_LCR_BCON_Pos)
#define	UART_LCR_PSEL_Pos				(4)
#define UART_LCR_PSEL_Msk				(0x3UL<<UART_LCR_PSEL_Pos)
#define	UART_LCR_PEN_Pos				(3)
#define UART_LCR_PEN_Msk				(0x1UL<<UART_LCR_PEN_Pos)
#define	UART_LCR_SBS_Pos				(2)
#define UART_LCR_SBS_Msk				(0x1UL<<UART_LCR_SBS_Pos)
#define	UART_LCR_WLS_Pos				(0)
#define UART_LCR_WLS_Msk				(0x3UL<<UART_LCR_WLS_Pos)

/*------MCR----------------------------------------------------------*/
#define	UART_MCR_XOFFS_Pos				(7)
#define UART_MCR_XOFFS_Msk				(0x1UL<<UART_MCR_XOFFS_Pos)
#define	UART_MCR_IREN_Pos				(6)
#define UART_MCR_IREN_Msk				(0x1UL<<UART_MCR_IREN_Pos)
#define	UART_MCR_MLBM_Pos				(4)
#define UART_MCR_MLBM_Msk				(0x1UL<<UART_MCR_MLBM_Pos)
#define	UART_MCR_RTS_Pos				(1)
#define UART_MCR_RTS_Msk				(0x1UL<<UART_MCR_RTS_Pos)

/*------LSR----------------------------------------------------------*/
#define	UART_LSR_RXFE_Pos				(7)
#define UART_LSR_RXFE_Msk				(0x1UL<<UART_LSR_RXFE_Pos)
#define	UART_LSR_TEMT_Pos				(6)
#define UART_LSR_TEMT_Msk				(0x1UL<<UART_LSR_TEMT_Pos)
#define	UART_LSR_THRE_Pos				(5)
#define UART_LSR_THRE_Msk				(0x1UL<<UART_LSR_THRE_Pos)
#define	UART_LSR_BI_Pos					(4)
#define UART_LSR_BI_Msk					(0x1UL<<UART_LSR_BI_Pos)
#define	UART_LSR_FE_Pos					(3)
#define UART_LSR_FE_Msk					(0x1UL<<UART_LSR_FE_Pos)
#define	UART_LSR_PE_Pos					(2)
#define UART_LSR_PE_Msk					(0x1UL<<UART_LSR_PE_Pos)
#define	UART_LSR_OE_Pos					(1)
#define UART_LSR_OE_Msk					(0x1UL<<UART_LSR_OE_Pos)
#define	UART_LSR_RDR_Pos				(0)
#define UART_LSR_RDR_Msk				(0x1UL<<UART_LSR_RDR_Pos)

/*------MSR----------------------------------------------------------*/
#define	UART_MSR_CTS_Pos				(4)
#define UART_MSR_CTS_Msk				(0x1UL<<UART_MSR_CTS_Pos)
#define	UART_MSR_DCTS_Pos				(0)
#define UART_MSR_DCTS_Msk				(0x1UL<<UART_MSR_DCTS_Pos)

/*------EFR----------------------------------------------------------*/
#define	UART_EFR_AUTOCTS_Pos			(7)
#define UART_EFR_AUTOCTS_Msk			(0x1UL<<UART_EFR_AUTOCTS_Pos)
#define	UART_EFR_AUTORTS_Pos			(6)
#define UART_EFR_AUTORTS_Msk			(0x1UL<<UART_EFR_AUTORTS_Pos)
#define	UART_EFR_AUTOIEN_Pos			(4)
#define UART_EFR_AUTOIEN_Msk			(0x1UL<<UART_EFR_AUTOIEN_Pos)
#define	UART_EFR_TXSWFC_Pos				(2)
#define UART_EFR_TXSWFC_Msk				(0x3UL<<UART_EFR_TXSWFC_Pos)
#define	UART_EFR_RXSWFC_Pos				(0)
#define UART_EFR_RXSWFC_Msk				(0x3UL<<UART_EFR_RXSWFC_Pos)

/* =========================================================================================================================== */
/* ================                                           I2C0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief I2C0 Decription (I2C0)
  */

typedef struct {                                /*!< (@ 0x48000000) I2C0 Structure                                             */
  __IOM uint32_t  CONSET;                    /*!< (@ 0x00000000) I2CCONSET Description                                      */
  __OM  uint32_t  CONCLR;                    /*!< (@ 0x00000004) I2CCONCLR Description                                      */
  __IM  uint32_t  STAT;                      /*!< (@ 0x00000008) I2CSTAT Description                                        */
  __IOM uint32_t  DAT;                       /*!< (@ 0x0000000C) I2CDAT Description                                         */
  __IOM uint32_t  CLK;                       /*!< (@ 0x00000010) I2CCLK Description                                         */
  __IOM uint32_t  ADR0;                      /*!< (@ 0x00000014) I2CADR0 Description                                        */
  __IOM uint32_t  ADM0;                      /*!< (@ 0x00000018) I2CADM0 Description                                        */
  __IOM uint32_t  XADR0;                     /*!< (@ 0x0000001C) I2CXADR0 Description                                       */
  __IOM uint32_t  XADM0;                     /*!< (@ 0x00000020) I2CXADM0 Description                                       */
  __OM  uint32_t  RST;                       /*!< (@ 0x00000024) I2CRST Description                                         */
  __IOM uint32_t  ADR1;                      /*!< (@ 0x00000028) I2CADR1 Description                                        */
  __IOM uint32_t  ADM1;                      /*!< (@ 0x0000002C) I2CADM1 Description                                        */
  __IOM uint32_t  ADR2;                      /*!< (@ 0x00000030) I2CADR2 Description                                        */
  __IOM uint32_t  ADM2;                      /*!< (@ 0x00000034) I2CADM2 Description                                        */
  __IOM uint32_t  ADR3;                      /*!< (@ 0x00000038) I2CADR3 Description                                        */
  __IOM uint32_t  ADM3;                      /*!< (@ 0x0000003C) I2CADM3 Description                                        */
} I2C0_Type;                                    /*!< Size = 64 (0x40)                                                          */

/*------CONSET---------------------------------------------------------------*/
#define	I2C_CONSSET_GCF_Pos				(8)
#define I2C_CONSSET_GCF_Msk				(0x1UL<<I2C_CONSSET_GCF_Pos)
#define	I2C_CONSSET_I2CIE_Pos			(7)
#define I2C_CONSSET_I2CIE_Msk			(0x1UL<<I2C_CONSSET_I2CIE_Pos)
#define	I2C_CONSSET_I2CEN_Pos			(6)
#define I2C_CONSSET_I2CEN_Msk			(0x1UL<<I2C_CONSSET_I2CEN_Pos)
#define	I2C_CONSSET_STA_Pos				(5)
#define I2C_CONSSET_STA_Msk				(0x1UL<<I2C_CONSSET_STA_Pos)
#define	I2C_CONSSET_STO_Pos				(4)
#define I2C_CONSSET_STO_Msk				(0x1UL<<I2C_CONSSET_STO_Pos)
#define	I2C_CONSSET_SI_Pos				(3)
#define I2C_CONSSET_SI_Msk				(0x1UL<<I2C_CONSSET_SI_Pos)
#define	I2C_CONSSET_AA_Pos				(2)
#define I2C_CONSSET_AA_Msk				(0x1UL<<I2C_CONSSET_AA_Pos)
#define	I2C_CONSSET_XADRF_Pos			(1)
#define I2C_CONSSET_XADRF_Msk			(0x1UL<<I2C_CONSSET_XADRF_Pos)
#define	I2C_CONSSET_ADRF_Pos			(0)
#define I2C_CONSSET_ADRF_Msk			(0x1UL<<I2C_CONSSET_ADRF_Pos)
/*------CONCLR---------------------------------------------------------------*/
#define	I2C_CONSCLR_I2CIEC_Pos			(7)
#define I2C_CONSCLR_I2CIEC_Msk			(0x1UL<<I2C_CONSCLR_I2CIEC_Pos)
#define	I2C_CONSCLR_I2CENC_Pos			(6)
#define I2C_CONSCLR_I2CEMC_Msk			(0x1UL<<I2C_CONSCLR_I2CENC_Pos)
#define	I2C_CONSCLR_STAC_Pos			(5)
#define I2C_CONSCLR_STAC_Msk			(0x1UL<<I2C_CONSCLR_STAC_Pos)
#define	I2C_CONSCLR_SIC_Pos				(3)
#define I2C_CONSCLR_SIC_Msk				(0x1UL<<I2C_CONSCLR_SIC_Pos)
#define	I2C_CONSCLR_AAC_Pos				(2)
#define I2C_CONSCLR_AAC_Msk				(0x1UL<<I2C_CONSCLR_AAC_Pos)
/*------STAT---------------------------------------------------------------*/
#define	I2C_STAT_STATUS_Pos				(2)
#define I2C_STAT_STATUS_Msk				(0x1FUL<<I2C_STAT_STATUS_Pos)


/* =========================================================================================================================== */
/* ================                                           SSP0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief SSP0 Decription (SSP0)
  */

typedef struct {                                /*!< (@ 0x43800000) SSP0 Structure                                             */
  __IOM uint32_t  CON;                       /*!< (@ 0x00000000) SSPCON Description                                         */
  __IM  uint32_t  STAT;                      /*!< (@ 0x00000004) SSPSTAT Description                                        */
  __IOM uint32_t  DAT;                       /*!< (@ 0x00000008) SSPDAT Description                                         */
  __IOM uint32_t  CLK;                       /*!< (@ 0x0000000C) SSPCLK Description                                         */
  __IOM uint32_t  IMSC;                      /*!< (@ 0x00000010) SSPIMSC Description                                        */
  __IM  uint32_t  RIS;                       /*!< (@ 0x00000014) SSPRIS Description                                         */
  __IM  uint32_t  MIS;                       /*!< (@ 0x00000018) SSPMIS Description                                         */
  __OM  uint32_t  ICLR;                      /*!< (@ 0x0000001C) SSPICLR Description                                        */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  CSCR;                      /*!< (@ 0x00000028) SSPCSCR Description                                        */
} SSP0_Type;                                    /*!< Size = 44 (0x2c)                                                          */

/*------CON---------------------------------------------------------------*/
#define	SSP_CON_LBM_Pos				(11)
#define SSP_CON_LBM_Msk				(0x1UL<<SSP_CON_LBM_Pos)
#define	SSP_CON_SSPEN_Pos			(10)
#define SSP_CON_SSPEN_Msk			(0x1UL<<SSP_CON_SSPEN_Pos)
#define	SSP_CON_MS_Pos				(9)
#define SSP_CON_MS_Msk				(0x1UL<<SSP_CON_MS_Pos)
#define	SSP_CON_SOD_Pos				(8)
#define SSP_CON_SOD_Msk				(0x1UL<<SSP_CON_SOD_Pos)
#define	SSP_CON_CPH_Pos				(7)
#define SSP_CON_CPH_Msk				(0x1UL<<SSP_CON_CPH_Pos)
#define	SSP_CON_CPO_Pos				(6)
#define SSP_CON_CPO_Msk				(0x1UL<<SSP_CON_CPO_Pos)
#define	SSP_CON_FRF_Pos				(4)
#define SSP_CON_FRF_Msk				(0x3UL<<SSP_CON_FRF_Pos)
#define	SSP_CON_DSS_Pos				(0)
#define SSP_CON_DSS_Msk				(0xFUL<<SSP_CON_DSS_Pos)
/*------STAT---------------------------------------------------------------*/
#define	SSP_STAT_BSY_Pos			(4)
#define SSP_STAT_BSY_Msk			(0x1UL<<SSP_STAT_BSY_Pos)
#define	SSP_STAT_RFF_Pos			(3)
#define SSP_STAT_RFF_Msk			(0x1UL<<SSP_STAT_RFF_Pos)
#define	SSP_STAT_RNE_Pos			(2)
#define SSP_STAT_RNE_Msk			(0x1UL<<SSP_STAT_RNE_Pos)
#define	SSP_STAT_TNF_Pos			(1)
#define SSP_STAT_TNF_Msk			(0x1UL<<SSP_STAT_TNF_Pos)
#define	SSP_STAT_TFE_Pos			(0)
#define SSP_STAT_TFE_Msk			(0x1UL<<SSP_STAT_TFE_Pos)
/*------CSCR---------------------------------------------------------------*/
#define	SSP_CSCR_SPH_Pos			(4)
#define SSP_CSCR_SPH_Msk			(0x1UL<<SSP_CSCR_SPH_Pos)
#define	SSP_CSCR_SWCS_Pos			(3)
#define SSP_CSCR_SWCS_Msk			(0x1UL<<SSP_CSCR_SWCS_Pos)
#define	SSP_CSCR_SWSEL_Pos			(2)
#define SSP_CSCR_SWSEL_Msk			(0x1UL<<SSP_CSCR_SWSEL_Pos)

/* =========================================================================================================================== */
/* ================                                           ADC0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief ADC0 Decription (ADC0)
  */

typedef struct {                                /*!< (@ 0x43000000) ADC0 Structure                                             */
  __IOM uint32_t  ADCCON;                       /*!< (@ 0x00000000) ADCCON Description                                         */
  __IOM uint32_t  ADCCON2;                      /*!< (@ 0x00000004) ADCCON2 Description                                        */
  __IOM uint32_t  ADCHWTG;                      /*!< (@ 0x00000008) ADCHWTG Description                                        */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  ADCSCAN;                      /*!< (@ 0x00000010) ADCSCAN Description                                        */
  __IOM uint32_t  ADCCMP0;                      /*!< (@ 0x00000014) ADCCMP0 Description                                        */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  ADCIMSC;                      /*!< (@ 0x0000001C) ADCIMSC Description                                        */
  __IM  uint32_t  ADCRIS;                       /*!< (@ 0x00000020) ADCRIS Description                                         */
  __IM  uint32_t  ADCMIS;                       /*!< (@ 0x00000024) ADCMIS Description                                         */
  __OM  uint32_t  ADCICLR;                      /*!< (@ 0x00000028) ADCICLR Description                                        */
  __IOM uint32_t  ADCLOCK;                      /*!< (@ 0x0000002C) ADCLOCK Description                                        */
  __IM  uint32_t  RESERVED2[20];
	__IM  uint32_t  ADCDATA[31];

} ADC0_Type;                                    /*!< Size = 252 (0xfc)                                                         */

/*------CON----------------------------------------------------------------*/
#define	ADC0_CON_ADCICHS_Pos		(16)
#define ADC0_CON_ADCICHS_Msk		(0x7UL<<ADC0_CON_ADCICHS_Pos)
#define	ADC0_CON_ADCEN_Pos			(4)
#define ADC0_CON_ADCEN_Msk			(0x1UL<<ADC0_CON_ADCEN_Pos)
#define	ADC0_CON_ADcms_Pos			(3)
#define ADC0_CON_ADcms_Msk			(0x1UL<<ADC0_CON_ADcms_Pos)
#define	ADC0_CON_ADCDIV_Pos			(0)
#define ADC0_CON_ADCDIV_Msk			(0x7UL<<ADC0_CON_ADCDIV_Pos)
/*------CON2----------------------------------------------------------------*/
#define	ADC0_CON2_ADCST_Pos			(7)
#define ADC0_CON2_ADCST_Msk			(0x1UL<<ADC0_CON2_ADCST_Pos)

/*------HWTG----------------------------------------------------------------*/
#define	ADC0_HWTG_ADCEXT0TEN_Pos	(17)
#define ADC0_HWTG_ADCEXT0TEN_Msk	(0x1UL<<ADC0_HWTG_ADCEXT0TEN_Pos)
#define	ADC0_HWTG_ADCEXT0TES_Pos	(16)
#define ADC0_HWTG_ADCEXT0TES_Msk	(0x1UL<<ADC0_HWTG_ADCEXT0TES_Pos)
#define	ADC0_HWTG_ADCINTTGEN_Pos	(15)
#define ADC0_HWTG_ADCINTTGEN_Msk	(0x1UL<<ADC0_HWTG_ADCINTTGEN_Pos)
#define	ADC0_HWTG_ADCINTTGSS_Pos	(12)
#define ADC0_HWTG_ADCINTTGSS_Msk	(0x7UL<<ADC0_HWTG_ADCINTTGSS_Pos)

/*------CMP0----------------------------------------------------------------*/
#define	ADC0_CMP0_CMP0EN_Pos		(31)
#define ADC0_CMP0_CMP0EN_Msk		(0x1UL<<ADC0_CMP0_CMP0EN_Pos)
#define	ADC0_CMP0_CMP0O_Pos			(30)
#define ADC0_CMP0_CMP0O_Msk			(0x1UL<<ADC0_CMP0_CMP0O_Pos)
#define	ADC0_CMP0_CMP0COND_Pos		(28)
#define ADC0_CMP0_CMP0COND_Msk		(0x1UL<<ADC0_CMP0_CMP0COND_Pos)
#define	ADC0_CMP0_CMP0MCNT_Pos		(24)
#define ADC0_CMP0_CMP0MCNT_Msk		(0xFUL<<ADC0_CMP0_CMP0MCNT_Pos)
#define	ADC0_CMP0_CMP0CHS_Pos		(16)
#define ADC0_CMP0_CMP0CHS_Msk		(0x1FUL<<ADC0_CMP0_CMP0CHS_Pos)
#define	ADC0_CMP0_CMP0DATA_Pos		(0)
#define ADC0_CMP0_CMP0DATA_Msk		(0xFFFUL<<ADC0_CMP0_CMP0CHS_Pos)
/*------IMSC----------------------------------------------------------------*/
#define	ADC0_IMSC_IMSC31_Pos		(31)
#define ADC0_IMSC_IMSC31_Msk		(0x1UL<<ADC0_IMSC_IMSC31_Pos)

/*------RIS-----------------------------------------------------------------*/
#define	ADC0_RIS_RIS31_Pos			(31)
#define ADC0_RIS_RIS31_Msk			(0x1UL<<ADC0_RIS_RIS31_Pos)
/*------MIS-----------------------------------------------------------------*/
#define	ADC0_MIS_MIS31_Pos			(31)
#define ADC0_MIS_MIS31_Msk			(0x1UL<<ADC0_MIS_MIS31_Pos)
/*------ICLR-----------------------------------------------------------------*/
#define	ADC0_ICLR_ICLR31_Pos		(31)
#define ADC0_ICLR_ICLR31_Msk		(0x1UL<<ADC0_ICLR_ICLR31_Pos)

/* =========================================================================================================================== */
/* ================                                           ADC1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief ADC1 Decription (ADC1)
  */

typedef struct {                                /*!< (@ 0x4D800000) ADC1 Structure                                             */
  __IOM uint32_t  ADCCON;                       /*!< (@ 0x00000000) ADCCON Description                                         */
  __IOM uint32_t  ADCCON2;                      /*!< (@ 0x00000004) ADCCON2 Description                                        */
  __IOM uint32_t  ADCHWTG;                      /*!< (@ 0x00000008) ADCHWTG Description                                        */
  __IOM uint32_t  ADCEPWMTGDLY;                 /*!< (@ 0x0000000C) ADCPWMTGDLY Description                                    */
  __IOM uint32_t  ADCSCAN;                      /*!< (@ 0x00000010) ADCSCAN Description                                        */
  __IOM uint32_t  ADCCMP0;                      /*!< (@ 0x00000014) ADCCMP0 Description                                        */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  ADCIMSC;                      /*!< (@ 0x0000001C) ADCIMSC Description                                        */
  __IM  uint32_t  ADCRIS;                       /*!< (@ 0x00000020) ADCRIS Description                                         */
  __IM  uint32_t  ADCMIS;                       /*!< (@ 0x00000024) ADCMIS Description                                         */
  __OM  uint32_t  ADCICLR;                      /*!< (@ 0x00000028) ADCICLR Description                                        */
  __IOM uint32_t  ADCLOCK;                      /*!< (@ 0x0000002C) ADCLOCK Description                                        */
  __IOM uint32_t  ADCCHEPWM;                    /*!< (@ 0x00000030) ADCCHEPWM Description                                      */
  __IOM uint32_t  ADCCHPTG0;                    /*!< (@ 0x00000034) ADCCHPTG0 Description                                      */
  __IOM uint32_t  ADCCHPTG1;                    /*!< (@ 0x00000038) ADCCHPTG1 Description                                      */
  __IM  uint32_t  RESERVED1[17];
	__IM  uint32_t  ADCDATA[31];
} ADC1_Type;                                    /*!< Size = 252 (0xfc)                                                         */

/*------CON----------------------------------------------------------------*/
#define ADC1_CON_ADCRST_Pos             (31)
#define ADC1_CON_ADCRST_Msk             (0x1UL<<ADC1_CON_ADCRST_Pos)
#define ADC1_CON_ADCCONVER_Pos          (25)
#define ADC1_CON_ADCCONVER_Msk          (0x1UL<<ADC1_CON_ADCCONVER_Pos)
#define ADC1_CON_ADCCALERR_Pos          (24)
#define ADC1_CON_ADCCALERR_Msk          (0x1UL<<ADC1_CON_ADCCALERR_Pos)
#define ADC1_CON_ADCCONVERRCLR_Pos      (21)
#define ADC1_CON_ADCCONVERRCLR_Msk      (0x1UL<<ADC1_CON_ADCCONVERRCLR_Pos)
#define ADC1_CON_ADCCALERRCLR_Pos       (20)
#define ADC1_CON_ADCCALERRCLR_Msk       (0x1UL<<ADC1_CON_ADCCALERRCLR_Pos)
#define ADC1_CON_ADCICHS_Pos            (16)
#define ADC1_CON_ADCICHS_Msk            (0x7UL<<ADC1_CON_ADCICHS_Pos)
#define ADC1_CON_ADCSS_Pos              (14)
#define ADC1_CON_ADCSS_Msk              (0x1UL<<ADC1_CON_ADCSS_Pos)
#define ADC1_CON_ADCSHT_Pos             (12)
#define ADC1_CON_ADCSHT_Msk             (0x3UL<<ADC1_CON_ADCSHT_Pos)
#define ADC1_CON_ADCEN_Pos              (4)
#define ADC1_CON_ADCEN_Msk              (0x1UL<<ADC1_CON_ADCEN_Pos)
#define ADC1_CON_ADCMS_Pos              (3)
#define ADC1_CON_ADCMS_Msk              (0x1UL<<ADC1_CON_ADCMS_Pos)
#define ADC1_CON_ADCDIV_Pos             (0)
#define ADC1_CON_ADCDIV_Msk             (0x7UL<<ADC1_CON_ADCMS_Pos)
/*------CON2----------------------------------------------------------------*/
#define ADC1_CON2_ADCST_Pos             (7)
#define ADC1_CON2_ADCST_Msk             (0x1UL<<ADC1_CON2_ADCST_Pos)
#define ADC1_CON2_ADCCALCONV_Pos        (1)
#define ADC1_CON2_ADCCALCONV_Msk        (0x1UL<<ADC1_CON2_ADCCALCONV_Pos)
#define ADC1_CON2_ADCCALEN_Pos          (0)
#define ADC1_CON2_ADCCALEN_Msk          (0x1UL<<ADC1_CON2_ADCCALEN_Pos)
/*------HWTG----------------------------------------------------------------*/
#define	ADC1_HWTG_ADCEXTEN_Pos			(17)
#define ADC1_HWTG_ADCEXTEN_Msk			(0x1UL<<ADC1_HWTG_ADCEXTEN_Pos)
#define	ADC1_HWTG_ADCEXTES_Pos			(16)
#define ADC1_HWTG_ADCEXTES_Msk			(0x1UL<<ADC1_HWTG_ADCEXTES_Pos)
#define	ADC1_HWTG_ADCINTTGEN_Pos		(15)
#define ADC1_HWTG_ADCINTTGEN_Msk		(0x1UL<<ADC1_HWTG_ADCINTTGEN_Pos)
#define	ADC1_HWTG_ADCINTTGSS_Pos		(12)
#define ADC1_HWTG_ADCINTTGSS_Msk		(0x7UL<<ADC1_HWTG_ADCINTTGSS_Pos)
#define	ADC1_HWTG_ADCPTG1EN_Pos			(9)
#define ADC1_HWTG_ADCPTG1EN_Msk			(0x1UL<<ADC1_HWTG_ADCPTG1EN_Pos)
#define	ADC1_HWTG_ADCPTG0EN_Pos			(8)
#define ADC1_HWTG_ADCPTG0EN_Msk			(0x1UL<<ADC1_HWTG_ADCPTG0EN_Pos)
#define	ADC1_HWTG_ADCEPWMTEN_Pos		(7)
#define ADC1_HWTG_ADCEPWMTEN_Msk		(0x1UL<<ADC1_HWTG_ADCEPWMTEN_Pos)
#define	ADC1_HWTG_ADCEPWMTSS_Pos		(4)
#define ADC1_HWTG_ADCEPWMTSS_Msk		(0x7UL<<ADC1_HWTG_ADCEPWMTSS_Pos)
#define	ADC1_HWTG_ADCEPWMTPS_Pos		(0)
#define ADC1_HWTG_ADCPEWMTPS_Msk		(0x3UL<<ADC1_HWTG_ADCEPWMTPS_Pos)

/*------CMP----------------------------------------------------------------*/
#define	ADC1_CMP_ADCCMPEN_Pos			(31)
#define ADC1_CMP_ADCCMPEN_Msk			(0x1UL<<ADC1_CMP_ADCCMPEN_Pos)
#define	ADC1_CMP_ADCCMPO_Pos			(30)
#define ADC1_CMP_ADCCMPO_Msk			(0x1UL<<ADC1_CMP_ADCCMPO_Pos)
#define	ADC1_CMP_ADCCMPCOND_Pos			(28)
#define ADC1_CMP_ADCCMPCOND_Msk			(0x1UL<<ADC1_CMP_ADCCMPCOND_Pos)
#define	ADC1_CMP_ADCCMPMCNT_Pos			(24)
#define ADC1_CMP_ADCCMPMCNT_Msk			(0xFUL<<ADC1_CMP_ADCCMPMCNT_Pos)
#define	ADC1_CMP_ADCCMPCHS_Pos			(16)
#define ADC1_CMP_ADCCMPCHS_Msk			(0x1FUL<<ADC1_CMP_ADCCMPCHS_Pos)
#define	ADC1_CMP_ADCCMPDATA_Pos			(0)
#define ADC1_CMP_ADCCMPDATA_Msk			(0xFFFUL<<ADC1_CMP_ADCCMPCHS_Pos)

/*------IMSC----------------------------------------------------------------*/
#define	ADC1_IMSC_IMSC31_Pos			(31)
#define ADC1_IMSC_IMSC31_Msk			(0x1UL<<ADC1_IMSC_IMSC31_Pos)
/*------RIS-----------------------------------------------------------------*/
#define	ADC1_RIS_RIS31_Pos				(31)
#define ADC1_RIS_RIS31_Msk				(0x1UL<<ADC1_RIS_RIS31_Pos)
/*------MIS-----------------------------------------------------------------*/
#define	ADC1_MIS_MIS31_Pos				(31)
#define ADC1_MIS_MIS31_Msk				(0x1UL<<ADC1_MIS_MIS31_Pos)
/*------ICLR----------------------------------------------------------------*/
#define	ADC1_ICLR_ICLR31_Pos			(31)
#define ADC1_ICLR_ICLR31_Msk			(0x1UL<<ADC1_ICLR_ICLR31_Pos)

/* =========================================================================================================================== */
/* ================                                            OP                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief OP Decription (OP)
  */

typedef struct {                                /*!< (@ 0x4C800000) OP Structure                                               */
  __IOM uint32_t  CON0;                      /*!< (@ 0x00000000) OP0CON0 Description                                        */
  __IOM uint32_t  CON1;                      /*!< (@ 0x00000004) OP0CON1 Description                                        */
  __IOM uint32_t  ADJE;                      /*!< (@ 0x00000008) OP0ADJE Description                                        */
} OP_Type;                                      /*!< Size = 40 (0x28)                                                          */

/*------CON0----------------------------------------------------------------*/
#define	OPA_CON0_EN_Pos					(7)
#define OPA_CON0_EN_Msk					(0x1UL<<OPA_CON0_EN_Pos)
#define	OPA_CON0_COFM_Pos				(6)
#define OPA_CON0_COFM_Msk				(0x1UL<<OPA_CON0_COFM_Pos)
#define	OPA_CON0_FIL_Pos				(5)
#define OPA_CON0_FIL_Msk				(0x1UL<<OPA_CON0_FIL_Pos)
#define	OPA_CON0_OS_Pos					(4)
#define OPA_CON0_OS_Msk					(0x1UL<<OPA_CON0_OS_Pos)
#define	OPA_CON0_NS_Pos					(2)
#define OPA_CON0_NS_Msk					(0x3UL<<OPA_CON0_NS_Pos)
#define	OPA_CON0_PS_Pos					(0)
#define OPA_CON0_PS_Msk					(0x3UL<<OPA_CON0_PS_Pos)
/*------CON1----------------------------------------------------------------*/
#define	OPA_CON1_OUT_Pos				(7)
#define OPA_CON1_OUT_Msk				(0x1UL<<OPA_CON1_OUT_Pos)
#define	OPA_CON1_CRS_Pos				(6)
#define OPA_CON1_CRS_Msk				(0x1UL<<OPA_CON1_CRS_Pos)
#define	OPA_CON1_ADJ_Pos				(0)
#define OPA_CON1_ADJ_Msk				(0x1FUL<<OPA_CON1_ADJ_Pos)

/*---------------------- PGA  Manger Controller -------------------------*/
typedef struct
{					
	__IO  uint32_t CON;
} PGA_Type;

/*------PGA----------------------------------------------------------------*/
#define	PGA_CON_EN_Pos					(15)
#define PGA_CON_EN_Msk					(0x1UL<<PGA_CON_EN_Pos)
#define	PGA_CON_GS_Pos					(12)
#define PGA_CON_GS_Msk					(0x7UL<<PGA_CON_GS_Pos)
#define	PGA_CON_RGS_Pos					(11)
#define PGA_CON_RGS_Msk					(0x1UL<<PGA_CON_RGS_Pos)
#define	PGA_CON_OS_Pos					(8)
#define PGA_CON_OS_Msk					(0x3UL<<PGA_CON_OS_Pos)
#define	PGA_CON_PS_Pos					(4)
#define PGA_CON_PS_Msk					(0x3UL<<PGA_CON_PS_Pos)
/* =========================================================================================================================== */
/* ================                                           ACMP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief ACMP Decription (ACMP)
  */

typedef struct {                                /*!< (@ 0x4D000000) ACMP Structure                                             */
  __IOM uint32_t  C0CON0;                       /*!< (@ 0x00000000) C0CON0 Description                                         */
  __IOM uint32_t  C0CON1;                       /*!< (@ 0x00000004) C0CON1 Description                                         */
  __IOM uint32_t  C0CON2;                       /*!< (@ 0x00000008) C0CON2 Description                                         */
  __IOM uint32_t  C0ADJE;                       /*!< (@ 0x0000000C) C0ADJE Description                                         */
  __IOM uint32_t  C1CON0;                       /*!< (@ 0x00000010) C1CON0 Description                                         */
  __IOM uint32_t  C1CON1;                       /*!< (@ 0x00000014) C1CON1 Description                                         */
  __IOM uint32_t  C1CON2;                       /*!< (@ 0x00000018) C1CON2 Description                                         */
  __IOM uint32_t  C1ADJE;                       /*!< (@ 0x0000001C) C1ADJE Description                                         */
  __IOM uint32_t  CVRCON;                       /*!< (@ 0x00000020) CVRCON Description                                         */
  __IOM uint32_t  CEVCON;                       /*!< (@ 0x00000024) CVECON Description                                         */
  __IOM uint32_t  IMSC;                         /*!< (@ 0x00000028) IMSC Description                                           */
  __IM  uint32_t  RIS;                          /*!< (@ 0x0000002C) RIS Description                                            */
  __IM  uint32_t  MIS;                          /*!< (@ 0x00000030) MIS Description                                            */
  __OM  uint32_t  ICLR;                         /*!< (@ 0x00000034) ICLR Description                                           */
  __IOM uint32_t  LOCK;                         /*!< (@ 0x00000038) LOCK Description                                           */
} ACMP_Type;                                    /*!< Size = 60 (0x3c)                                                          */

/*------C0CON0----------------------------------------------------------------*/
#define	ACMP_C0CON0_EN_Pos					(15)
#define ACMP_C0CON0_EN_Msk					(0x1UL<<ACMP_C0CON0_EN_Pos)
#define	ACMP_C0CON0_COFM_Pos				(14)
#define ACMP_C0CON0_COFM_Msk				(0x1UL<<ACMP_C0CON0_COFM_Pos)
#define	ACMP_C0CON0_N2GND_Pos				(13)
#define ACMP_C0CON0_N2GND_Msk				(0x1UL<<ACMP_C0CON0_N2GND_Pos)
#define	ACMP_C0CON0_PS_Pos					(4)
#define ACMP_C0CON0_PS_Msk					(0xFUL<<ACMP_C0CON0_PS_Pos)
#define	ACMP_C0CON0_NS_Pos					(0)
#define ACMP_C0CON0_NS_Msk					(0xFUL<<ACMP_C0CON0_NS_Pos)
/*------C0CON1----------------------------------------------------------------*/
#define	ACMP_C0CON1_OUT_Pos					(9)
#define ACMP_C0CON1_OUT_Msk					(0x1UL<<ACMP_C0CON1_OUT_Pos)
#define	ACMP_C0CON1_CRS_Pos					(8)
#define ACMP_C0CON1_CRS_Msk					(0x1UL<<ACMP_C0CON1_CRS_Pos)
#define	ACMP_C0CON1_ADJ_Pos					(0)
#define ACMP_C0CON1_ADJ_Msk					(0x1FUL<<ACMP_C0CON1_ADJ_Pos)
/*------C0CON2----------------------------------------------------------------*/
#define	ACMP_C0CON2_HYSLS_Pos				(12)
#define ACMP_C0CON2_HYSLS_Msk				(0x1UL<<ACMP_C0CON2_HYSLS_Pos)
#define	ACMP_C0CON2_HYSVS_Pos				(10)
#define ACMP_C0CON2_HYSVS_Msk				(0x3UL<<ACMP_C0CON2_HYSVS_Pos)
#define	ACMP_C0CON2_POS_Pos					(9)
#define ACMP_C0CON2_POS_Msk					(0x1UL<<ACMP_C0CON2_POS_Pos)
#define	ACMP_C0CON2_FE_Pos					(8)
#define ACMP_C0CON2_FE_Msk					(0x1UL<<ACMP_C0CON2_FE_Pos)
#define	ACMP_C0CON2_FS_Pos					(0)
#define ACMP_C0CON2_FS_Msk					(0xFUL<<ACMP_C0CON2_FS_Pos)

/*------C1CON0----------------------------------------------------------------*/
#define	ACMP_C1CON0_EN_Pos					(15)
#define ACMP_C1CON0_EN_Msk					(0x1UL<<ACMP_C1CON0_EN_Pos)
#define	ACMP_C1CON0_COFM_Pos				(14)
#define ACMP_C1CON0_COFM_Msk				(0x1UL<<ACMP_C1CON0_COFM_Pos)
#define	ACMP_C1CON0_N2GND_Pos				(13)
#define ACMP_C1CON0_N2GND_Msk				(0x1UL<<ACMP_C1CON0_N2GND_Pos)
#define	ACMP_C1CON0_PS_Pos					(4)
#define ACMP_C1CON0_PS_Msk					(0xFUL<<ACMP_C1CON0_PS_Pos)
#define	ACMP_C1CON0_NS_Pos					(0)
#define ACMP_C1CON0_NS_Msk					(0xFUL<<ACMP_C1CON0_NS_Pos)
/*------C1CON1----------------------------------------------------------------*/
#define	ACMP_C1CON1_OUT_Pos					(9)
#define ACMP_C1CON1_OUT_Msk					(0x1UL<<ACMP_C1CON1_OUT_Pos)
#define	ACMP_C1CON1_CRS_Pos					(8)
#define ACMP_C1CON1_CRS_Msk					(0x1UL<<ACMP_C1CON1_CRS_Pos)
#define	ACMP_C1CON1_ADJ_Pos					(0)
#define ACMP_C1CON1_ADJ_Msk					(0x1FUL<<ACMP_C1CON1_ADJ_Pos)
/*------C1CON2----------------------------------------------------------------*/
#define	ACMP_C1CON2_HYSLS_Pos				(12)
#define ACMP_C1CON2_HYSLS_Msk				(0x3UL<<ACMP_C1CON2_HYSLS_Pos)
#define	ACMP_C1CON2_HYSVS_Pos				(10)
#define ACMP_C1CON2_HYSVS_Msk				(0x3UL<<ACMP_C1CON2_HYSVS_Pos)
#define	ACMP_C1CON2_POS_Pos					(9)
#define ACMP_C1CON2_POS_Msk					(0x1UL<<ACMP_C1CON2_POS_Pos)
#define	ACMP_C1CON2_FE_Pos					(8)
#define ACMP_C1CON2_FE_Msk					(0x1UL<<ACMP_C1CON2_FE_Pos)
#define	ACMP_C1CON2_FS_Pos					(0)
#define ACMP_C1CON2_FS_Msk					(0xFUL<<ACMP_C1CON2_FS_Pos)

/*------CVRCON----------------------------------------------------------------*/
#define	ACMP_CVRCON_CSVR_Pos				(4)
#define ACMP_CVRCON_CSVR_Msk				(0x3UL<<ACMP_CVRCON_CSVR_Pos)
#define	ACMP_CVRCON_CVS_Pos					(0)
#define ACMP_CVRCON_CVS_Msk					(0xFUL<<ACMP_CVRCON_CVS_Pos)

/*------CEVCON----------------------------------------------------------------*/
#define	ACMP_CEVCON_EVE1_Pos				(5)
#define ACMP_CEVCON_EVE1_Msk				(0x1UL<<ACMP_CEVCON_EVE1_Pos)
#define	ACMP_CEVCON_EVE0_Pos				(4)
#define ACMP_CEVCON_EVE0_Msk				(0x1UL<<ACMP_CEVCON_EVE0_Pos)
#define	ACMP_CEVCON_EVS1_Pos				(2)
#define ACMP_CEVCON_EVS1_Msk				(0x3UL<<ACMP_CEVCON_EVS1_Pos)
#define	ACMP_CEVCON_EVS0_Pos				(0)
#define ACMP_CEVCON_EVS0_Msk				(0x3UL<<ACMP_CEVCON_EVS0_Pos)
/*------IMSC------------------------------------------------------------------*/
#define	ACMP_IMSC_C1IF_Pos					(1)
#define ACMP_IMSC_C1IF_Msk					(0x1UL<<ACMP_IMSC_C1IF_Pos)
#define	ACMP_IMSC_C0IF_Pos					(0)
#define ACMP_IMSC_C0IF_Msk					(0x1UL<<ACMP_IMSC_C0IF_Pos)
/*------RIS------------------------------------------------------------------*/
#define	ACMP_RIS_C1IF_Pos					(1)
#define ACMP_RIS_C1IF_Msk					(0x1UL<<ACMP_RIS_C1IF_Pos)
#define	ACMP_RIS_C0IF_Pos					(0)
#define ACMP_RIS_C0IF_Msk					(0x1UL<<ACMP_RIS_C0IF_Pos)
/*------MIS------------------------------------------------------------------*/
#define	ACMP_MIS_C1IF_Pos					(1)
#define ACMP_MIS_C1IF_Msk					(0x1UL<<ACMP_MIS_C1IF_Pos)
#define	ACMP_MIS_C0IF_Pos					(0)
#define ACMP_MIS_C0IF_Msk					(0x1UL<<ACMP_MIS_C0IF_Pos)
/*------ICLR------------------------------------------------------------------*/
#define	ACMP_ICLR_C1IF_Pos					(1)
#define ACMP_ICLR_C1IF_Msk					(0x1UL<<ACMP_ICLR_C1IF_Pos)
#define	ACMP_ICLR_C0IF_Pos					(0)
#define ACMP_ICLR_C0IF_Msk					(0x1UL<<ACMP_ICLR_C0IF_Pos)

/* =========================================================================================================================== */
/* ================                                            FMC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief FMC Decription (FMC)
  */

typedef struct {                                /*!< (@ 0x49800000) FMC Structure                                              */
  __IOM uint32_t  CON;                       /*!< (@ 0x00000000) FMCCON Description                                         */
  __IOM uint32_t  ADR;                       /*!< (@ 0x00000004) FMCADR Description                                         */
  __IOM uint32_t  DAT;                       /*!< (@ 0x00000008) FMCDAT Description                                         */
  __IOM uint32_t  CMD;                       /*!< (@ 0x0000000C) FMCCMD Description                                         */
  __IOM uint32_t  LOCK;                      /*!< (@ 0x00000010) FMCLOCK Description                                        */
  __IM  uint32_t  RESERVED[3];
  __IOM uint32_t  CRCEA;                     /*!< (@ 0x00000020) FMCCRCEA Description                                       */
  __IOM uint32_t  CRCIN;                     /*!< (@ 0x00000024) FMCCRCIN Description                                       */
  __IOM uint32_t  CRCD;                      /*!< (@ 0x00000028) FMCCRCD Description                                        */
} FMC_Type;                                     /*!< Size = 44 (0x2c)                                                          */

/*------CON------------------------------------------------------------------*/
#define	FMC_CON_BUSY_Pos					(5)
#define FMC_CON_BUSY_Msk					(0x1UL<<FMC_CON_BUSY_Pos)
#define	FMC_CON_ISPS_Pos					(4)
#define FMC_CON_ISPS_Msk					(0x1UL<<FMC_CON_ISPS_Pos)

/* =========================================================================================================================== */
/* ================                                            UID                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief UID Decription (UID)
  */

typedef struct {                                /*!< (@ 0x18000000) UID Structure                                              */
  __IM  uint32_t  RESERVED;
  __IM  uint32_t  UID0;                         /*!< (@ 0x00000004) UID0 Description                                           */
  __IM  uint32_t  UID1;                         /*!< (@ 0x00000008) UID1 Description                                           */
  __IM  uint32_t  UID2;                         /*!< (@ 0x0000000C) UID2 Description                                           */
} UID_Type;                                     /*!< Size = 16 (0x10)                                                          */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define SYSCON_BASE                 0x50000000UL
#define GPIO0_BASE                  0x52000000UL
#define GPIO1_BASE                  0x52800000UL
#define GPIO2_BASE                  0x53000000UL
#define GPIO3_BASE                  0x53800000UL
#define GPIO4_BASE                  0x54000000UL
#define WDT_BASE                    0x47800000UL
#define WWDT_BASE                   0x41800000UL
#define CRC_BASE                    0x4A000000UL
#define HWDIV_BASE                  0x55000000UL
#define TIMER0_BASE                 0x46800000UL
#define TIMER1_BASE                 0x46800100UL
#define CCP_BASE                    0x42800000UL
#define EPWM_BASE                   0x4A800000UL
#define UART0_BASE                  0x44800000UL
#define UART1_BASE                  0x45000000UL
#define I2C0_BASE                   0x48000000UL
#define SSP0_BASE                   0x43800000UL
#define ADC0_BASE                   0x43000000UL
#define ADC1_BASE                   0x4D800000UL
#define OP0_BASE                    0x4C800000UL
#define OP1_BASE                    0x4C80000CUL
#define PGA0_BASE                   0x4C800018UL
#define PGA1_BASE                   0x4C800024UL
#define ACMP_BASE                   0x4D000000UL
#define FMC_BASE                    0x49800000UL
#define UID_BASE                    0x18000000UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define SYSCON                      ((SYSCON_Type*)            SYSCON_BASE)
#define GPIO0                       ((GPIO_Type*)             GPIO0_BASE)
#define GPIO1                       ((GPIO_Type*)             GPIO1_BASE)
#define GPIO2                       ((GPIO_Type*)             GPIO2_BASE)
#define GPIO3                       ((GPIO_Type*)             GPIO3_BASE)
#define GPIO4                       ((GPIO_Type*)             GPIO4_BASE)
#define WDT                         ((WDT_Type*)               WDT_BASE)
#define WWDT                        ((WWDT_Type*)              WWDT_BASE)
#define CRC                         ((CRC_Type*)               CRC_BASE)
#define HWDIV                       ((HWDIV_Type*)             HWDIV_BASE)
#define TIMER0                      ((TIMER0_Type*)            TIMER0_BASE)
#define TIMER1                      ((TIMER0_Type*)            TIMER1_BASE)
#define CCP                         ((CCP_Type*)               CCP_BASE)
#define EPWM                        ((EPWM_Type*)              EPWM_BASE)
#define UART0                       ((UART0_Type*)             UART0_BASE)
#define UART1                       ((UART0_Type*)             UART1_BASE)
#define I2C                         ((I2C0_Type*)              I2C0_BASE)
#define SSP                         ((SSP0_Type*)              SSP0_BASE)
#define ADC0                        ((ADC0_Type*)              ADC0_BASE)
#define ADC1                        ((ADC1_Type*)              ADC1_BASE)
#define OPA0                        ((OP_Type*)                OP0_BASE)
#define OPA1                        ((OP_Type*)                OP1_BASE)
#define PGA0                        ((PGA_Type*)               PGA0_BASE)
#define PGA1                        ((PGA_Type*)               PGA1_BASE)
#define ACMP                        ((ACMP_Type*)              ACMP_BASE)
#define FMC                         ((FMC_Type*)               FMC_BASE)
#define UID                         ((UID_Type*)               UID_BASE)

/******************************************************************************/
/*                         Peripheral header files                            */
/******************************************************************************/
#include "system.h"
#include "gpio.h"
#include "acmp.h"
#include "adc0.h"
#include "adc1.h"
#include "ccp.h"
#include "crc.h"
#include "epwm.h"
#include "gpio.h"
#include "hwdiv.h"
#include "i2c.h"
#include "opa.h"
#include "pga.h"
#include "ssp.h"
#include "timer.h"
#include "uart.h"
#include "wdt.h"
#include "wwdt.h"
#include "fmc.h"
/** @} */ /* End of group Device_Peripheral_declaration */


#ifdef __cplusplus
}
#endif

#endif /* CMS32M55XX_H */


/** @} */ /* End of group CMS32M55xx */

/** @} */ /* End of group CMS Ltd. */
